Browsing Computer Science and Automation (CSA) by Author "Patil, Adarsh"
Now showing items 1-1 of 1
-
Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures
Patil, AdarshIntegrated Heterogeneous System (IHS) processors pack throughput-oriented GPGPUs along-side latency-oriented CPUs on the same die sharing certain resources, e.g., shared last level cache, network-on-chip (NoC), and the ...