Browsing Computer Science and Automation (CSA) by Advisor "Amrutur, Bharadwaj"
Now showing items 1-2 of 2
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Power Efficient Last Level Cache For Chip Multiprocessors
(2015-09-09)The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip cache has become very significant. We explore various techniques ... -
Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors
(2009-03-09)A Large instruction window is a key requirement to exploit greater Instruction Level Parallelism in out-of-order superscalar processors. Along with the instruction window size, the size of various other structures including ...