Browsing Division of Electrical, Electronics, and Computer Science (EECS) by Advisor "Amrutur, Bharadwaj"
Now showing items 1-20 of 25
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0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology
With increasing demand of IoT devices, medical devices, remote sensors; the design of low power analog interface is becoming focus. Generally, for low frequency applications the Sigma Delta ADCs are used due to their very ... -
Bitrate Reduction Techniques for Low-Complexity Surveillance Video Coding
(2017-09-26)High resolution surveillance video cameras are invaluable resources for effective crime prevention and forensic investigations. However, increasing communication bandwidth requirements of high definition surveillance videos ... -
Conformal Active Sheets
(2017-12-16)Stretchable Electronics is an emerging class of electronics that allow electronics to be bent, conform, ex and stretch while still retaining its full functionality. Other than bending, existing and conforming, adding ... -
Design and Characterization of SRAMs for Ultra Dynamic Voltage Scalable (U-DVS) Systems
(2017-11-29)The ever expanding range of applications for embedded systems continues to offer new challenges (and opportunities) to chip manufacturers. Applications ranging from exciting high resolution gaming to routine tasks like ... -
First-Spike-Latency Codes : Significance, Relation to Neuronal Network Structure and Application to Physiological Recordings
(2018-04-12)Over the last decade advances in multineuron simultaneous recording techniques have produced huge amounts of data. This has led to the investigation of probable temporal relationships between spike times of neurons as ... -
Functional Safety Analysis Techniques for Integrated Circuits Used in Cyber-Physical Systems
Integrated Circuits (ICs) are used to realize multitude of real life systems. These real life systems have ICs interacting with physical systems (this combination being referred to as cyber-physical systems or hybrid ... -
Imitation Learning Techniques for Robot Manipulation
Robots that can operate in unstructured environments and collaborate with humans play a major role in raising productivity and living standards as societies age. Unlike the robots currently used in industrial settings for ... -
Low Power and Low Area Techniques for Neural Recording Application
(2018-02-23)Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for ... -
Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters
(2017-09-07)There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor ... -
Low Power LO Generation Based On Frequency Multiplication Technique
(2008-08-27)TO achieve high level of integration in order to reduce cost, heterodyne architecture has made way for low-IF and zero-IF (direct conversion) receiver architectures. However, a very serious issue in implementing both zero ... -
Low Power Receiver Architecture And Algorithms For Low Data Rate Wireless Personal Area Networks
(2013-09-03)Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed in the node. The thesis proposes receiver architecture and algorithms ... -
Nature-inspired Algorithms for Automated Deployment of Outdoor IoT Networks
A vast majority of the Internet of Things (IoT) devices will be connected in a topology where the edge-devices push data to a local gateway, which forwards the data to a cloud for further processing. In sizeable outdoor ... -
NoC Design & Optimization of Multicore Media Processors
(2018-03-22)Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling ... -
Power Efficient Last Level Cache For Chip Multiprocessors
(2015-09-09)The number of processor cores and on-chip cache size has been increasing on chip multiprocessors (CMPs). As a result, leakage power dissipated in the on-chip cache has become very significant. We explore various techniques ... -
Power Scaling Mechanism for Low Power Wireless Receivers
(2018-06-26)LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all ... -
Random Local Delay Variability : On-chip Measurement And Modeling
(2011-01-18)This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a ... -
Scalable Low Power Issue Queue And Store Queue Design For Superscalar Processors
(2009-03-09)A Large instruction window is a key requirement to exploit greater Instruction Level Parallelism in out-of-order superscalar processors. Along with the instruction window size, the size of various other structures including ... -
Statistical Leakage Analysis Framework Using Artificial Neural Networks Considering Process And Environmental Variations
(2013-07-03)Leakage current and process variations are two primary hurdles in modern VLSI design. It depends exponentially on process and environmental parameters and hence small variations in these result in a large spread in leakage ... -
Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector
(2011-01-18)Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation ... -
Techniques For Low Power Motion Estimation In Video Encoders
(2013-02-12)This thesis looks at hardware algorithms that help reduce dynamic power dissipation in video encoder applications. Computational complexity of motion estimation and the data traffic between external memory and the video ...