• Login
    View Item 
    •   etd@IISc
    • Division of Electrical, Electronics, and Computer Science (EECS)
    • Electronic Systems Engineering (ESE)
    • View Item
    •   etd@IISc
    • Division of Electrical, Electronics, and Computer Science (EECS)
    • Electronic Systems Engineering (ESE)
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Random Local Delay Variability : On-chip Measurement And Modeling

    View/Open
    G23404.pdf (1.774Mb)
    Date
    2011-01-18
    Author
    Das, Bishnu Prasad
    Metadata
    Show full item record
    Abstract
    This thesis focuses on random local delay variability measurement and its modeling. It explains a circuit technique to measure the individual logic gate delay in silicon to study within-die variation. It also suggests a Process, Voltage and Temperature (PVT)-aware gate delay model for voltage and temperature scalable linear Statistical Static Timing Analysis (SSTA). Technology scaling allows packing billions of transistors inside a single chip. However, it is difficult to fabricate very small transistor with deterministic characteristic which leads to variations. Transistor level random local variations are growing rapidly in each technology generation. However, there is requirement of quantification of variation in silicon. We propose an all-digital circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form based on a reconfigurable ring oscillator structure. A test chip is fabricated in 65nm technology node to show the feasibility of the technique. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. The huge random delay variation in silicon motivates the inclusion of random local process parameters in delay model. In today’s low power design with multiple supply domain leads to non-uniform supply profile. The switching activity across the chip is not uniform which leads to variation of temperature. Accurate timing prediction motivates the necessity of Process, Voltage and Temperature (PVT) aware delay model. We use neural networks, which are well known for their ability to approximate any arbitrary continuous function. We show how the model can be used to derive sensitivities required for voltage and temperature scalable linear SSTA for an arbitrary voltage and temperature point. Using the voltage and temperature scalable linear SSTA on ISCAS 85 benchmark shows promising results with average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.65% and errors in predicting the 99% and 1% probability point are 1.31% and 1% respectively with respect to SPICE.
    URI
    https://etd.iisc.ac.in/handle/2005/1008
    Collections
    • Electronic Systems Engineering (ESE) [166]

    Related items

    Showing items related by title, author, creator and subject.

    • Design and Analysis of Integrated Optic Waveguide Delay Line Phase Shifters for Microwave Photonic Application 

      Honnungar, Rajini V (2018-04-23)
      Microwave Photonics(MWP) has been defined as the study of photonic devices which operate at microwave frequencies and also their applications to microwave and optical systems. One or more electrical signals at microwave ...
    • Delay Differentiation By Balancing Weighted Queue Lengths 

      Chakraborty, Avijit (2017-05-04)
      Scheduling policies adopted for statistical multiplexing should provide delay differentiation between different traffic classes, where each class represents an aggregate traffic of individual applications having same ...
    • Maleimide Based Materials for Organic Light-Emitting Diodes (OLEDs) 

      Sharma, Nidhi (2018-06-11)
      Maleimide based highly luminescent material Cbz-MI with donor acceptor donor (D-A-D) backbone has been synthesized and characterized. An organic light emitting diode fabricated using this material as emitting layer exhibited ...

    etd@IISc is a joint service of SERC & J R D Tata Memorial (JRDTML) Library || Powered by DSpace software || DuraSpace
    Contact Us | Send Feedback | Thesis Templates
    Theme by 
    Atmire NV
     

     

    Browse

    All of etd@IIScCommunities & CollectionsTitlesAuthorsAdvisorsSubjectsBy Thesis Submission DateThis CollectionTitlesAuthorsAdvisorsSubjectsBy Thesis Submission Date

    My Account

    LoginRegister

    etd@IISc is a joint service of SERC & J R D Tata Memorial (JRDTML) Library || Powered by DSpace software || DuraSpace
    Contact Us | Send Feedback | Thesis Templates
    Theme by 
    Atmire NV