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Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors

dc.contributor.advisorGovindarajan, R
dc.contributor.authorValluri, Madhavi Gopal
dc.date.accessioned2011-11-16T05:13:48Z
dc.date.accessioned2018-07-31T05:08:55Z
dc.date.available2011-11-16T05:13:48Z
dc.date.available2018-07-31T05:08:55Z
dc.date.issued2011-11-16
dc.date.submitted1999
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/1532
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/1959/G15406-Abs.pdfen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG23229en_US
dc.subjectCompiling (Electronic Computers)en_US
dc.subjectMultiprocessorsen_US
dc.subjectInstruction Schedulingen_US
dc.subjectCompilersen_US
dc.subjectRegister Allocationen_US
dc.subjectMachine Modelsen_US
dc.subjectInstruction-Level Parallelism (ILP)en_US
dc.subjectVery Long Instruction Word (VLIW) Processorsen_US
dc.subjectModulo-Variable Expansion (MVE)en_US
dc.subjectSensitive Schedulingen_US
dc.subject.classificationComputer Scienceen_US
dc.titleEvaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processorsen_US
dc.typeThesisen_US
dc.degree.nameMSc Enggen_US
dc.degree.levelMastersen_US
dc.degree.disciplineFaculty of Engineeringen_US


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