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Compiler Techniques For Code Size And Power Reduction For Embedded Processors

dc.contributor.advisorGovindarajan, R
dc.contributor.authorSarvani, V V N S
dc.date.accessioned2011-04-28T09:32:58Z
dc.date.accessioned2018-07-31T04:39:58Z
dc.date.available2011-04-28T09:32:58Z
dc.date.available2018-07-31T04:39:58Z
dc.date.issued2011-04-28
dc.date.submitted2004
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/1135
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/1489/G18678-Abs.pdfen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG18678en_US
dc.subjectMicroprocessorsen_US
dc.subjectEmbedded Systemsen_US
dc.subjectCompilersen_US
dc.subjectEmbedded Processorsen_US
dc.subject.classificationComputer Scienceen_US
dc.titleCompiler Techniques For Code Size And Power Reduction For Embedded Processorsen_US
dc.typeThesisen_US
dc.degree.nameMSc Enggen_US
dc.degree.levelMastersen_US
dc.degree.disciplineFaculty of Engineeringen_US


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