Browsing by Advisor "Jacob, Matthew T"
Now showing items 1-14 of 14
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Cache Coherence State Based Replacement Policies
(2018-07-14)Cache replacement policies can play a pivotal role in the overall performance of a system by preserving data locality and thus limiting the o -chip accesses. In a shared memory system, a cache coherence protocol is necessary ... -
Characterization of Divergence resulting from Workload, Memory and Control-Flow behavior in GPGPU Applications
GPGPUs have emerged as high-performance computing platforms and are used for boosting the performance of general non-graphics applications from various scientifi c domains. These applications span varied areas like social ... -
Efficient Dynamic Automatic Memory Management And Concurrent Kernel Execution For General-Purpose Programs On Graphics Processing Units
(2017-04-28)Modern supercomputers now use accelerators to achieve their performance with the most widely used accelerator being the Graphics Processing Unit (GPU). However, achieving the performance potential of systems that combine ... -
Efficient Online Path Profiling
(2009-06-05)Most dynamic program analysis techniques such as profile-driven compiler optimizations, software testing and runtime property checking infer program properties by profiling one or more executions of a program. Unfortunately, ... -
Experiments with the pentium Performance monitoring counters
(Indian Institute of Science, 2005-02-11)Performance monitoring counters are implemented in most recent microprocessors. In this thesis, we describe various performance measurement experiments for a program and a system that we conducted on a Linux operating ... -
Experiments With Unix Process Schedulers
(2012-05-09) -
Improving The Communication Performance Of I/O Intensive And Communication Intensive Application In Cluster Computer Systems
(2009-04-13)Cluster computer systems assembled from commodity off-the-shelf components have emerged as a viable and cost-effective alternative to high-end custom parallel computer systems.In this thesis, we investigate how scalable ... -
Loop Transformations for Multi-/Many-Core Architectures using Machine Learning
Loop transformation techniques such as loop tiling, loop interchange and unroll-and-jam help expose better coarse-grain and fine-grain data-level parallelisms as well as exploit data locality. These transformations are ... -
Low Power Test Methodology For SoCs : Solutions For Peak Power Minimization
(2013-09-13)Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power ... -
Performance Measurement Of A Java Virtual Machine
(2011-11-16) -
Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation
(2018-01-10)Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the ... -
Superscalar Processor Models Using Statistical Learning
(2009-06-24)Processor architectures are becoming increasingly complex and hence architects have to evaluate a large design space consisting of several parameters, each with a number of potential settings. In order to assist in guiding ...