| dc.description.abstract | This thesis explores the potential of analog computing to meet the growing computational demands of power-intensive applications and evolving algorithms. While analog computation offers significant advantages in power efficiency and computational density by leveraging device physics, its widespread adoption has been hindered by several key challenges: non-modular design practices, lack of robustness comparable to digital standard cells, limited technology, and bias scalability, and the absence of automated synthesis methodologies.
To address these challenges, this work identifies and extends to generalize a novel mathematical framework called Margin Propagation (MP), which enables the development of Standard Analog Cells (S-ACs). The S-AC unit cell implements the MP mathematical function, which serves as the fundamental building block for modular and scalable analog computation.
Composite Standard Analog Cells (Composite S-AC) are designed for each application domain and validated using novel hardware and software approaches proposed in this thesis. These Composite S-ACs are modular and scalable across operating conditions and process technology nodes. Dimensional scalability is introduced by developing a code-based automation framework for high-level synthesis. These features, combined with precision tunability achieved from the Generalized Margin Propagation (GMP) framework, make it a suitable Standard Analog Cell framework.
To validate the silicon feasibility of this approach, these composite Standard Analog Cells are implemented on a custom-built Field Programmable Analog Array (FPAA) called ARYABHAT. This in-house FPAA, designed on the 180nm technology node, employs a S-AC-based crossbar architecture with programmable switches, allowing the realization of diverse applications and demonstrating the practical viability of the proposed methodology.
The versatility of the S-AC is showcased through three application domains: XOR-SAT solvers for communication decoders, probabilistic computing, and machine learning.
An XOR-SAT formulation is proposed for the design of a Low-Density Parity Check (LDPC) decoder based on a novel MP-based optimization function. Compared to the standard Sum-Product Algorithm (SPA), the proposed algorithm achieves superior performance while significantly reducing computational and hardware complexity. The MP-based algorithm culminates in an energy-efficient mixed-mode CMOS circuit implementation using S-AC. The decoding algorithm is partitioned into digital and analog domains, each implemented on digital/analog programmable arrays. A commercial FPGA and ARYABHAT FPAA operate in tandem, forming a hybrid FPGA-FPAA platform that validates the silicon performance of the proposed LDPC decoder.
This work demonstrates a complete top-down flow from mathematical formulation through algorithm development to circuit design and implementation.
This thesis then introduces a novel concept of Probabilistic Soft-Gates designed using the S-AC circuits, which include Soft-AND, Soft-OR, Soft-XOR, and their inverted versions. These gates enable the implementation of Bayesian inference tasks, LDPC decoding, and some non-probabilistic applications, such as image filtering. Contrary to the traditional LDPC decoding algorithms, which approximate probabilistic XOR operations using deterministic mathematical transformations, this work re-engineers the algorithm in the probabilistic domain, allowing a more natural and efficient implementation of the decoding process. Unlike the XOR-SAT LDPC design, which goes from algorithm to circuits, this work provides a bottom-up approach using the circuits in algorithms.
The third application is in machine learning. The thesis proposes mathematical functions such as multiplication, non-linear activation functions, winner-take-all, etc., which are essential in machine learning applications. The case study of an Artificial Neural Network showcases the scalability and energy efficiency of the S-AC-based design. This work provides an idea of designing the S-AC circuits based on the expected characteristic curve of the mathematical function and plugging it back into existing architectures.
While the above applications highlight the versatility of the S-AC, the analog design remains time-intensive due to custom design and routing requirements. To address this bottleneck, this thesis proposes a novel automated high-level synthesis flow, which translates high-level design specifications into S-AC-based SPICE netlists, enabling rapid functional validation and significantly reducing design time. This automation brings analog design closer to the efficiency of digital ASIC flows, especially for dimensionally large designs.
In summary, this thesis lays the foundation for the broader adoption of a synthesizable, scalable, and diversified analog computing framework based on the S-AC. It unlocks new possibilities for high-performance, low-power systems while supporting the development of error-resilient analog systems that remain invariant to transistor operating conditions, device non-idealities, and process technologies, thus pushing the boundaries of modern computing paradigms. | en_US |
