Programmable nonlinear ADCS -some new techniques

Abstract

New Program mable Successive Approximation NADCs In this class of NADCs, the main emphasis has been to achieve digital programmability by using optimal-sized ROM, or PLS in the successive approximation loop while at the same time optimizing the conversion speed. A comparison of the main features of the NADCs developed is given in Table 6. 1. From this Table, it is clear that these NADCs offer a trade-off among their different characteristics. For example, the hybrid NADC has the highest conversion speed, but its hardware complexity is much higher, whereas the ROM-prefetch NADC is slower but has the advantage of hardware simplicity. Also, while it is easy to program the piecewise linear approximation NADC, its operating speed is much lower than that of the other NADCs, and also it is applicable only if the nonlinear characteristic can be approximated by a finite number of linear segments. Factors like these decide the choice of an NADC for a given application by a judicious consideration of its characteristics. The highlights of these NADCs are as follows: a) N A D C U sin g O ptim al-Sized R OM In this NADC, optimal-sized ROM is used in place of SAR. A new technique of using LSB of the ROM address to hold the comparator output is utilized to minimize the ROM size. As compared to the NADC of [36], considerable reduction in ROM size is possible here,e. g. , 96% for PCM codec application. This leads to appreciable reduction in the die area required for the fabrication of the NADC in IC form