Investigations on Extending the Linear Modulation Range of Multilevel Inverter Fed Induction Motor Drives

Abstract

Multilevel inverter topologies find extensive industrial and automobile applications due to their utilization of lower voltage-rated switches and enhanced harmonic performance. Incorporating Pulse Width Modulation (PWM) techniques further reduces their switching frequency requirements. These combined advantages position MLIs as a practical substitute for regular two-level inverters. Despite their benefits, MLIs have their limitations, too, and one prominent limitation is their linear modulation range (LMR). The LMR of an inverter refers to the range within which it can generate a voltage space vector with a circular locus. The linear modulation range of conventional MLIs, when operated with standard Space Vector Pulse Width Modulation (SVPWM) strategies, is limited to a voltage space vector radius of 0.866Vdc, resulting in a maximum peak fundamental phase voltage of 0.577Vdc. Beyond this limit lies the overmodulation region, where they operate in six-step mode, creating a hexagonal locus for the voltage space vector. This results in lower-order harmonic dominance in the phase voltage. Even though the maximum peak fundamental phase voltage magnitude of the inverter can reach up to 0.637Vdc, the existence of lower-order harmonics creates unwanted vibrations and jerks in the motor shaft long with harmonic losses. This restricts the linear speed range of the Induction Motor (IM) to 90.5% of its full base speed. This research proposes three inverter topologies extending the linear modulation range to the full base speed of an induction motor by generating a maximum peak fundamental phase voltage of 0.637Vdc without any lower-order harmonics. Thus, the linear modulation range is extended throughout the conventional overmodulation region, eliminating the lower-order harmonic troubles expected in a conventional inverter. Chapter 2 suggests a twenty-four switch, three-level Neutral Point Clamped Inverter-based power circuit for the first time. In contrast, Chapter 3 advances further, presenting a five-level, twenty-four-switch inverter structure. Chapter 4 furthers the research, putting forward an eighteen-switch, five-level reduced switch count inverter topology. All the proposal offers extended linear modulation range till full base speed. The research outcomes eliminate the need for costly and bulky filters for over-modulation region operation. The proposed power circuits can be easily implemented using off-the-shelf inverter IC packages making them suitable candidates for the power VLSI era. All these low switch count power circuits have a direct implication on reducing both the initial and operating costs of the system. Enhanced reliability by means of the lower component count is yet another benefit. Various steady-state and transient experiments verified the research outcomes for their practicality. The suggestions' fault tolerance and dependence on the load power factor were also studied. The works discussed in Chapters 2 to 4 were simulated in MATLAB prior to their hardware implementation. The hardware studies using the prototypes built in lab verified the simulation results. DSP (TMS320F28335) and an FPGA (Xilinx Spartan 3 XC3S400) are used to implement the control modules in these works.