| dc.description.abstract | Nowadays, multilevel inverters (MLIs) have become a promising alternative to the twolevel inverter in medium voltage high-power applications such as motor drives, active power filters,
HVDC, electric vehicles, wind, and solar power generation. In the high-speed motor drives domain,
the motor speed reaches above the base speed region. The motor runs in the flux-weakening zone
above the designed base speed using either an open-loop variable frequency variable voltage
algorithm or a closed-loop field-oriented control algorithm. But, the maximum torque production
capability of the motor decreases substantially while it runs in the field-weakening zone. To increase
the maximum torque of the motor drive, the peak phase fundamental needs to be raised by enhancing
the DC-link utilisation of the inverter. The only possible way to increase DC bus utilisation for any
hexagonal Space Vector Structured (SVS) VSI is to operate the inverter in six-step mode. However, in
the six-step mode, the inverter yields square wave output voltages comprised of undesirable lower
order harmonics such as 5th,7th,11th and 13th etc., which causes low frequency torque ripple. The
low frequency torque ripple (such as 6th and 12th etc.) may eventually cause a breakdown of the
motor shaft at a higher speed, reducing the lifespan of the motor.
In the work of the thesis, the issues mentioned earlier are addressed so that the modulation range
can be increased linearly without the presence of lower order harmonics irrespective of load power
factor (p.f). In the first work, a hybrid nine level T-type inverter topology with extended DC bus
utilisation is proposed. An increase in the DC bus utilisation is possible by increasing the pole voltage
levels to ±(Vdc/2 + Vdc/8) using the H-bridge capacitor voltage during 11 level mode, and it is achieved
by adding an offset to sine reference. This offset is added so that all the capacitor voltages remain
regulated in the 11-level mode of operation. The aforementioned offset added PWM strategy
increases the peak phase fundamental voltage from 0.577Vdc to 0.625Vdc in the case of unity p.f load
and 0.6366Vdc for 0.82 p.f load with the proposed nine level inverter. The proposed inverter scheme
and its claim of increasing the peak phase fundamental voltage is experimentally validated in a
laboratory prototype. The second work presents a 10-level dual inverter scheme to extend the linear
modulation range (LMR) by using a unique space vector pulse width modulation (SVPWM) technique.
The 10-level inverter structure is formed using a 2-level inverter and an H-bridge (HB) in cascade from
one end and a floating capacitor-based 2-level inverter cascaded with an H-bridge from the other end
to drive an open-end winding induction motor (OEWIM). This proposed circuit structure yields a 9-
level SVS that can be further extended to a unique 10-level SVS by subtracting or adding the HB
capacitors voltages. All the HB capacitor voltages are balanced by using SV redundancy, where for
every vector points, there exists a pair of the opposite vector from HBs and secondary 2-level. The
claim of balancing the capacitor voltages throughout the whole modulation range is varied
experimentally in this paper. The third work presents a hybrid seven level dual inverter scheme with
increased LMR. The hybrid inverter structure is formed by supplying the load from the primary side
using a cascaded structure of a two-level inverter and H-bridge. A floating capacitor supplies the
secondary side of the load fed two-level inverter. The combination of primary two level SVS with
secondary two level SVS and primary three level SVS of HB form a seven level SVS that can further be
extended to an eight level hexagonal SVS. This structure was then reduced to a 12-sided 8-level SVS
to avoid exceeding motor phase voltage rating. Subsequently, using this eight level SVS in a unique
PWM mode, the proposed topology can increase the modulation range linearly from 0.577Vdc to
0.6366Vdc peak phase fundamental voltage for any load p.f. To balance HB capacitors voltages in this
work, a concept of indirect SV redundancy is used. The efficacy of the proposed inverter scheme is
verified through various experimental results at different steady state and transient condition. | en_US |
