Investigations on Polygonal Voltage Space Vector Structure generation with lower order harmonic suppression using switched capacitive filter throughout modulation range for Drive Applications

Abstract

Multilevel inverters (MLI) are widely used in a host of industrial applications ranging from renewable energy systems, to electric vehicles, to distributed generation. Due to the switching nature of the output voltage, MLI generate harmonics in output voltage at switching frequency. The harmonics in output voltage generate harmonic currents in the load, which may lead to losses in the system, and may also cause torque pulsations for motor drive applications. Hence, it is necessary to improve the harmonic performance (Total Harmonic Distortion-THD) of the output voltage. To improve the THD of the output voltage, passive filters may be incorporated to suppress the switching frequency harmonics. To optimize the component size in the filter, inverters are operated at high switching frequency. The high switching frequency in MLI generates electro-magnetic interference (EMI) and large dv/dt in the switching devices and motor load. Due to these drawbacks, the passive filtering solution is not very attractive. To overcome the aforementioned drawbacks, polygonal space vector structures have been proposed. This solution leads to generation of polygonal voltage space vector structures with sides greater than 6, in the over-modulation region. By switching on the vertices of dense space vector structure, lower order harmonics in phase voltage are suppressed with increased utilization of DC link voltage. Polygonal space vector structures can be generated by using a secondary inverter fed with a capacitive supply. The polygon is generated by superposition of the primary and secondary inverter space vectors. Polygonal space vector generation offers many advantages over conventional solutions. Polygonal space vector structures offer increased linear modulation range, which leads to maximum utilization of the DC link supply. In this scheme the main power delivery inverter fed with the active DC link supply is switched at low switching frequency. The reduced switching frequency reduces switching losses and reduces dv/dt. The secondary inverter is fed with a capacitive supply which is balanced at a fraction of the DC link voltage supply. The capacitive supply is balanced at it's nominal voltage during motoring/braking operation by using a novel capacitor balancing scheme. The presence of a single active supply to provide power for motoring operation reduces system complexity and facilitates four quadrant operation. The secondary inverter fed with low voltage capacitive supply is switched at high frequency for suppression of harmonics generated by low switching frequency primary inverter. The secondary inverter can be realized using low voltage semiconductor devices as the blocking voltage requirements for the secondary inverter are considerably lower. The secondary inverter does not provide any active power for motoring operation and hence acts as a switched capacitive filter. Compared to the conventional bulky passive filtering solutions, the switched capacitive filter is cost effective.