Investigations on Multilevel Voltage Space Vectors Generated by Stacked and Cascaded Basic Inverter Cells with Capacitor Voltage Control for Induction Motor Drives

Abstract

Induction motor drives (IMD) require a DC-AC inverter system to obtain variable frequency operation. Generally, IMD uses conventional 2-level inverters. The conventional 2-level inverter has its pole switching between zero and DC bus voltage. Thus, the switching in 2-level inverter results in high dv/dt in the inverter pole voltage. Also, the switches in the inverter need to block a full DC link voltage which increases the switching losses. These issues with drive scheme using 2-level inverter can be addressed by using multilevel inverters (MLI). Some of the frequently used MLI topologies include 3-level neutral point clamped (NPC), flying capacitor (FC) and cascaded H-bridges (CHB) inverters. But, by using FC inverter to generate more number of levels requires more number of floating capacitors while, using CHB inverter to generate more number of levels requires more number of isolated power supplies. The NPC inverters require more number of clamping diodes as number of level increases and also it suffers from neutral point voltage (NPV) deviations which results in using isolated DC sources or large value of stacked DC-link capacitance. Likewise, stacked MLI also uses stacking of DC-link capacitors to generate more number of levels and suffers from neutral point voltage deviation. In the first work, a method to control the NPV deviation is proposed for stacked MLI. The NPV is balanced instantaneously which enables the single DC-link operation of stacked MLI. The controlling of neutral point (NP) voltages are obtained by using low voltage capacitor fed cascaded H-bridge (CHB) per phase of symmetrical 6-phase induction machine (IM), which ensures zero current drawn from NP (at any given instant). The proposed method of controlling NPV is independent of loading, load power factor and modulation index. The method is validated using 7-level topology consists of 3 series connected DC-link capacitors with two neutral points fed from single DC source. The topology and PWM operation ensures that the NPV fluctuations in the 3 series connected charged capacitors are absent throughout the modulation index range. Further, the concept is extended to obtain common mode eliminated 7-level structure with NPV control. The generalization of this method for any stacked n-level inverter without NPV deviation is also proposed. The open loop V/f operation is performed on IM for various speeds and in transient state to support the above claims. In the second work, a new 7-level inverter topology is proposed. It is realised by cascading a 3-level T-Type inverter with 5-level active neutral point clamped inverter. The proposed topology uses low voltage semiconductor devices and floating capacitors which are balanced in every PWM switching cycle using pole voltage redundancies for every pole voltage levels. The balancing of capacitor voltages are independent of modulation index and load power factor. The topology forms two stacks at the front-end which uses individual symmetrical reduced DC sources. Further, the method proposed in the first part of the work is used to obtain the single DC-link operation with NPV control of two stacked capacitor. The topology is validated first using open loop V/f and then using the closed loop rotor field oriented control for IM. Further, the loss analysis shows that the topology has less switching as well as conduction loss as compared to some of the 7-level MLI reported in various literatures. In the third work, a 15-level (14 concentric) dodecagonal (12-sided) voltage space vector structure using stacked and cascaded MLI is proposed. It is generated by cascading 5-level capacitor fed CHB inverter (secondary inverter) with a 5-level stacked inverter (primary inverter). The active power is sourced only by the primary inverter and the secondary inverter acts as an active harmonic filter. The primary inverter works in a quasi-square mode throughout the modulation and high frequency switchings are shifted to low voltage CHBs, which reduces the switching losses. The proposed scheme has dense dodecagonal space vector structure which gives better harmonic performance as compared to other schemes generating dodecagonal space vector structures. The switching loss analysis is accomplished and shown that the scheme has less switching loss than conventional 2-level, 3-level and 5-level inverters. Due to 12-sided space vector structure the 6n+/-1 (‘n’ is odd) is highly suppressed which results in better performance and reduced low order filter requirements. The scheme is validated for open loop V/f control to obtain the steady and transient state performance.