| dc.description.abstract | In 2020, Apple introduced its most advanced laptop that has the A14 Bionic processor. The very first processor, Intel’s 4004, was launched in 1971 and had a transistor (the basic building block of a processor) density of ~ 205 transistors/mm2. Compared to that, Apple’s A14 Bionic processor comes with an astonishingly large ~ 125 million transistors/mm2. Such a remarkable evolution in silicon transistor technology has occurred in the last five decades. This has arguably been the most rapidly growing field in the 300,000 thousand years old history of modern humans.
Computational power, functionality and speed of a processor largely depend on the size of the transistor. Aggressive transistor scaling, based on Dennard’s law, in all aspects has resulted in today’s transistors with minimum feature size of 5 nm which is almost 2000 times smaller than that of the most primitive, commercially available transistors. Perpetual demand to perform high speed data processing and cost minimization has led to dramatic advancement in transistor design and process technology which has clearly served the purpose, so far. Our hunger for further improvement in data processing, especially in the era of Internet of Things (IoT) and big data, has kept us looking into the future of transistor scaling. Unfortunately, transistor size has started to hit a fundamental limit and highly scaled transistors with tens or hundreds of atoms are not able to satisfactorily process data. In other words, a transistor fabricated from the current state-of-the-art 5 nm process would fail to even operate like a transistor if it were further scaled down. Apparently, for further improvement in processing speed and functionality, it seems tough to move into the atomic regimes of transistor size as long as silicon is in use. Another way to achieve better performance of our systems is to stay with the already established silicon technology and focus on better system level integration of processors and/or come-up with a paradigm shift from using the current von-Neumann computer architecture to a more energy efficient one.
It turns out that atomically thin 2-dimensional (2D) materials can prove to successfully replace silicon in transistors, owing to their robustness against short channel effects which otherwise degrade performance of ultra-scaled silicon devices. In order to qualify 2D materials for a possible future technology, it is important to develop insights on them through a constant effort in form of fundamental as well as technological research. Although, moving from bulk silicon to 2D appears to be the right approach to realize further transistor scaling, it has been way too challenging to address and eventually solve three major challenges – large contact resistance, lack of industrially viable doping techniques and lack of large area single crystal growth methods, that prevent quick technology development on 2D materials for transistor applications.
More than 200 2D materials naturally occur, from which transition metal dichalcogenides (TMDCs) are so far considered to be most suitable for ultra-scaled transistors, owing to their non-zero finite electronic bandgap and large electron effective mass. Since the fabrication of first TMDC transistor in 2011, enormous effort has been put in to identify ways to solve concerns related to large contact resistance, polarity control through doping and wafer-scale single crystal growth. As a result, device-level optimizations on TMDCs have enabled highly effective contact, channel and dielectric engineering techniques to address underlying problems associated with TMDCs. One of these contact engineering techniques is H2S treatment of TMDCs at temperature much lower than that during growth process. Unlike most other techniques to degenerately dope the transistor which lead to improvement in drive current along with significantly degraded gate control and OFF state performance, the method to expose contacts and channel with H2S, developed during this work, turns out to have improved almost all aspects of transistor performance, besides being a dry and scalable process [1]. Remarkable ON state performance improvement has been realized along with orders of magnitude improvement in the drain current modulation of the transistor [1]. It is found that presence of unique chalcogen impurities at the contact and channel lead to much better overlap of atomic orbitals of TMDC and metal atoms which results in drastically improved carrier injection across the interface [1]. When the same contact engineering technique is used with tungsten diselenide (WSe2), the interface becomes greatly dependent on the metal contact in use [2]. Choice of contact turns out to be critical in the presence of Sulfur interstitial atom-induced unique gap states (DIGS), as these impurity atoms alter the nature of metal-induced gap states (MIGS) [2]. It is found that contacts to WSe2 can be realized selectively to obtain desirable transistor polarity. Owing to lack of implantation techniques for 2D TMDCs, doping and polarity control has remained a bottleneck for long. Realization of n and p-type transistors on the same substrate using this method could result in a complete CMOS fabrication process development on WSe2. The defect states added by H2S exposure, universally result in hole current improvement for all conventional TMDCs [3]. Extracting hole current from all TMDCs is not trivial especially in CVD-grown monolayer MoS2 due to its large bandgap and sulfur vacancy concentration. H2S induced sulfur interstitial defects are found to lie close to the valence band edge due to which fermi-level is pinned closer to valence band thereby reducing barrier height for hole conduction [3]. While one part of this work is focused on developing CMOS circuits on TMDCs using H2S treatment of contacts, exploring long-term electrical reliability of TMDC systems has also been an important part. So far, reliability studies on TMDCs have remained confined to studying ambient induced effects and standard high field phenomena like velocity saturation, avalanche breakdown, negative differential resistance etc. Such reports on reliability physics of TMDCs are not only limited but also restricted to observing breakdown and high field phenomena, instead of identifying progressive response to high-field and root cause of device performance degradation to eventual failure. In this work, TMDC FETs are subjected to long-term DC electrical stress to identify electrothermal transport induced material perturbations [4, 5]. Insights developed on low-field and high-field transport in TMDCs suggest that channel conductance improves when devices are stressed for long durations due to introduction of sulfur vacancy-like defects in the channel. Negative shift in threshold voltage and decrease in channel potential after electrical stress along with red shift in Raman out-of-plane mode and increase in trion formation, observed in photoluminescence spectra, point towards the fact that a prolonged transistor operation results in a piezoelectric response due to which weak hopping transport and enhanced screening of charged impurities are observed [4, 5, 6]. Classical interpretation of Raman spectra and channel potential measurements using kelvin probe force microscopy (KPFM) reveal that these defects are in fact perturbed Mo-S bonds [6]. Besides electrical transport, sufficient evidence of improved thermal transport through the channel is found [6]. Our findings trigger an interesting visualization of how TMDCs would naturally adapt, through piezoelectric response, to high-field electrical stress in a way that makes them better electrical and thermal conductors [6]. Remarkable similarities between long-term electrical stress and hysteresis induced resistance switching have been particularly encouraging. Both are found to have induced resistance switching in MoS2 [7]. Based on polarity dependent response to electrical stress, it is found that, MoS2 based RRAMs subjected to certain electrical stress conditions start exhibiting improved binary switching performance [7]. As a result, an electroforming method has been developed that triggers better binary memory switching characteristics. Moreover, charge transport mechanism in MoS2 based gated RRAMs along with forming voltage are found to influence resistance switching performance, substantially [7].
This work has broadly focused on improving contact and channel properties of TMDC based transistors, polarity control and hole current improvement followed by development of CMOS circuit fabrication process on TMDCs, especially WSe2, and developing insights on physics of material-device reliability and resistance switching in TMDCs. For TMDC transistor technology to flourish, it is important not only to fabricate and characterize devices and circuits but also to assess the reliability quotient. Long term device and circuit reliability of TMDCs has remained un-addressed and must be thoroughly understood if TMDC based electronics is to be pursued in future. Besides adding to technological advancement of 2D material electronics through realization of polarity specific devices and CMOS circuits using a scalable process, this work would significantly contribute to fundamental knowledge base for TMDCs by familiarizing the 2D community with the role of sulfur interstitial defects, self-adapting behavior of MoS2 against electrical stress and transport dependent resistance switching mechanism. | en_US |
