dc.contributor.advisor | Sambandan, Sanjiv | |
dc.contributor.author | Daniel, Sanil K | |
dc.date.accessioned | 2021-04-12T07:09:14Z | |
dc.date.available | 2021-04-12T07:09:14Z | |
dc.date.submitted | 2019 | |
dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/5050 | |
dc.description.abstract | Active matrix backplanes used in
at panel displays are prone to line faults (opens and
shorts) and pixel faults (poor transistor performance and parameter variations). These
faults could occur during fabrication or during operation. To improve the yield of a process
line, it is important that the backplanes be free of most forms of error. Thus the testing
of backplanes is a key aspect in the manufacturing chain.
To address this, several system have been reported using different methodologies. However
most of the technologies can only identify hard faults such as opens and shorts.
Moreover many techniques require the presence of the photonic system (eg:- light emitting
diode or liquid crystal display) integrated with the backplane. This thesis discuss the
development of a system that not only identi fies hard line faults but also soft faults such
as transistor parameter variations. The test system performs an electrical measurement in
the back plane. This thesis primarily discusses the technique for testing LCD back plane.
The LCD backplane pixels consists of a switch capacitor, with the TFT acting as the
switch. The general algorithm of testing is to write data in the pixel capacitor and read
out the charge for a given gate voltage applied to the pixel select TFT. This process is
repeated for a sequence of gate voltages. This results in the measurement of the time
averaged current(due to the discharging pixel capacitor) vs. gate voltage characteristics
for each pixel select switch of the display. The key parameters of the TFT can be extracted
from this plot. The thesis discussed the design and the development of the test system.
Experiments of back plane testing are performed on amorphous silicon TFT arrays
and experimental results and parameters extracted using the developed test system are
compared with measurements made on the TFT using the Keithley 4200 semiconductor parameter analyser. The parameters extracted by the test system corroborates well with
the parameters extracted by the Keithley 4200. While this thesis illustrates the technique
for a switch-capacitor circuit (LCD driver), it also discuss how the technique can be
adapted to light emitting diode (LED) based display pixel architectures | en_US |
dc.language.iso | en_US | en_US |
dc.relation.ispartofseries | ;G29836 | |
dc.rights | I grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part
of this thesis or dissertation | en_US |
dc.subject | back plane testing | en_US |
dc.subject | LED display | en_US |
dc.subject | TFT display | en_US |
dc.subject.classification | Research Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Other electrical engineering, electronics and photonics | en_US |
dc.title | Development of an Automated Test & Parameter Extraction Tool for Active Matrix Displays | en_US |
dc.type | Thesis | en_US |
dc.degree.name | PhD | en_US |
dc.degree.level | Doctoral | en_US |
dc.degree.grantor | Indian Institute of Science | en_US |
dc.degree.discipline | Engineering | en_US |