| dc.description.abstract | Multilevel inverters (MLI) are the most preferable alternatives for medium to
high voltage applications. It finds in many applications like traction drives, fans,
blowers, HVDC and FACTs etc. It offers many attractive features over a conventional
2-Level inverter like lower voltage stress across the power switches, lower dv=dt across the
load terminals, lesser EMI, lesser current and voltage total harmonics distortion (THD)
etc. In contrast to a 2-Level inverter, the output of a MLI produces many discrete steps
which makes the output voltage nearer to an ideal sine wave. This allows to reduce the
switching frequency in a MLI which in turn control the losses in the power switches in
a MLI. All these features make MLI superior compared to a 2-Level inverter in every
aspect. In modern days, the application of MLI in the field of medium to high power
AC motor drives becomes indispensable. There are many basic MLI schemes like Neutral
Point Clamped (NPC), Flying Capacitor (FC) and Cascaded H-Bridge (CHB) inverters.
These basic inverter scheme have many advantages and disadvantages over one another.
To mitigate the disadvantages of the basic MLI schemes, hybrid MLI schemes have been
presented in the literature. Also, the multilevel operation can be achieved using dual fed
inverter schemes where two inverters are being fed from either side of the open-end load.
With the increase in levels, basic MLI schemes require more number of components
like clamping diode (in case of NPC inverters), floating capacitors (in case of FC inverters)
and isolated DC-sources (in case of CHB inverter). The main objective behind developing
a new MLI scheme is to optimize the component counts and also increasing the reliability.
In this thesis, 5-Level reduced component count MLI schemes are proposed using a single
DC link. Usage of a single DC-link in a MLI scheme enables easy four quadrant operation.
Furthermore, the proposed schemes are more reliable compared to the basic MLI schemes.
In case of a fault in any of the floating bridges, the schemes can still be operated at rated
power of the drive. All the floating capacitor in these schemes are charged by the phase
current by employing a hysteresis controller. This feature eliminates the need of an extra
pre-charging circuit for the inverter. The floating capacitors are balanced in each PWM
cycle which enables to use low value capacitor even for high power applications.
For many safety critical applications it is extremely important that the reliability of
electric drives to fulfil certain safety norms, especially when human lives, environmental
damages or important economic losses are involved. Power electronic converters play an
important role in electrical drives where certain fault conditions such as open- or shortcircuit
can lead to potentially dangerous situations. In conventional multilevel inverters,
abnormal condition arises when a fault occur in the power switch, gate driver or any
of the discredited wire of the inverter. Reliable fault tolerant MLI schemes are usually
achieved by providing overrated or more reliable components, using redundant design
or adopting automatic changes in the control strategy in the event of partial failures in
the converter. In this thesis, a 5-Level fault tolerant scheme is presented using reduced
number of components compared to the basic MLI schemes. In the proposed scheme,
if the fault occurs in any of the power switch in the floating bridges, the inverter can
operate the drive without any interruption. After isolating the fault, the drive can be
operated at the full rated power. The faulty part of the inverter can be isolated seamlessly
during drive operation without introducing any transient in the phase voltage or current.
This is possible because the the supplied power to the load remains same before the fault
and after isolating the fault. Experimental results in the normal operating condition and
the fault mode of operation are presented for the inverter scheme. A capacitor balancing
algorithm is proposed using space vector redundancy and the capacitors are balanced in a
PWM cycle during the inverter operation at steady and transient states. The operation of
the inverter and the capacitor voltage balancing scheme is validated through experiments
at different frequencies of operation of the inverter.
The basic and most popular multilevel inverter schemes are NPC, FC and CHB.
With increase in the number pole voltage level, the NPC inverter requires more number
of clamping diodes. Also, the NPC inverter suffers from the neutral point balancing
problem at higher modulation indices. The neutral point voltage control becomes more
difficult with increase in the number of stacked DC-link capacitors. On the other hand, a
FC inverter requires more number of floating capacitors. The balancing of all the floating
capacitors by switching state redundancy requires a complex balancing algorithm. It
also causes an increase in switching loss. In case of a CHB inverter, more number of
isolated DC sources are required, which makes the system bulky and costlier. Also, the
usage of multiple DC-links make the regeneration operation of the drive difficult. In
this thesis, a reduced switch count (only using six switches per phase) 5-Level inverter
scheme is proposed using a single DC link for OEIM drive. In this scheme two inverters
are feeding OEIM from either side of the open stator windings. One inverter is a 3-Level
FC inverter and this inverter is supplied with a DC-link. It is the source of the active
power for the OEIM drive. The other inverter is a capacitor fed 2-Level inverter. The
DC-link to the capacitor voltage in the floating bridge is maintained at a ratio of 4:1. The
inverter scheme is controlled such that the 2-Level capacitor fed bridge acts as a switched
capacitive filter. So the active power being fed by the bridge is zero which maintains the
capacitor voltage irrespective of the load power factor. The generalization method is also
presented in the thesis to extend the proposed scheme to a n-Level inverter. Another
remarkable feature of the proposed scheme is the fault tolerant capability. In case of a
failure in the capacitor-fed floating bridge, the OEIM drive can still be operated with the
other inverter after bypassing the faulty bridge. To validate the proposed scheme, the
simulation and experimental results are presented during the drive operation at steady
and transient states. The fault tolerant capability of the inverter scheme is verified by
performing experiments during the fault in the capacitor fed bridge. The faulty bridge is
isolated from rest of the inverter without interrupting the drive operation.
A conventional 2-Level or a multilevel inverter operating in linear modulation range
in hexagonal space vector PWM, generates strong fundamental component and the harmonics
at the side band of the switching frequency. To obtain more fundamental voltage
at the phases, the inverter schemes need to operate in over-modulation region (i.e. generated
peak phase fundamental voltage greater than 0.577 times DC-link voltage). Inverter
operating in over-modulation region produces strong of component of fundamental with
the lower order harmonics (i.e. 5th, 7th, 11th etc.). This lower order harmonics produces
lower order torque pulsation in the motor shaft. Also, these harmonics causes extra losses
in the motor windings and decreases the efficiency of the drive system. The maximum
peak fundamental component can be obtained from an inverter during square mode of operation
is 0.637 time DC-link voltage. At this time (i.e. six-step mode operation) inverter
produces strong lower order harmonic components. In this thesis a hybrid MLI scheme is
proposed to extend the linear modulation range to the full base speed irrespective of the
load power factor without introducing lower order harmonics in the phase voltage. This
is achieved by boosting the DC-link voltage with a charged capacitor. At the same time
during PWM operation, the capacitor voltage is controlled by using redundant vectors.
Linearly increasing the modulation range to the full base speed from 0.577 to 0.637 times
DC-link voltage, is proposed for the first time in this work with PWM control throughout
the modulation range irrespective of the load power factor. Due to linearization of the
extended modulation range, the phase voltage does not contain any lower order harmonics.
The inverter operation and capacitor balancing technique is analyzed thoroughly.
The simulation and experimental results for unity and non-unity power factor loads are
presented in steady and transient states.
A 10kW, 50Hz, 415V, 3-phase induction motor is used and phase coil group end
connections are connected appropriately to configure the machine as a 3-phase open-end
winding induction motor. To perform experiments, open loop v=f and closed loop field
oriented controllers are employed. 100A, 1200V IGBT semiconductor half-bridge modules
(SKM-100GB-12T4) are used as the power switch for the inverter. Opto-isolated gate
drivers (M57962L) with desaturation protection are used for driving the IGBT switches.
The controller is implemented in a TMS320F28335 DSP. The analog signals (capacitor
voltages and phase currents) are fed to the ADC channel of the DSP. The generated
PWM pulses along with the capacitor voltage status and the current polarity are sent
to a FPGA (Xilinx SPARTAN-3 XC3S200). Based on these data received from DSP,
the FPGA produces the gate signals for all the IGBT switches. A dead time of 2 S is
provided in between complementary gate pulses.
With the advantages like reduced switch count, fault tolerant capability, single DC
supply requirement, extension of linear modulation range, linear control of the inverter
over the entire modulation range, lesser dv=dt stresses on devices and motor phase windings,
inherent capacitor balancing, the proposed inverter schemes can be considered as
good choice for medium voltage, high power motor drive applications. | en_US |
