| dc.description.abstract | Gallium Nitride (GaN) based high electron mobility transistors (HEMTs) are extensively
considered for power switching and RF applications by the virtue of their unique
properties. However, despite of its attractive performance/cost ratio, AlGaN/GaN HEMT
suffers from poor reliability which limits its penetration in the ever-growing power device
market. Therefore, reliability of AlGaN/GaN HEMT has become a topic of intense
research. In last one decade, the long-term reliability of GaN devices, has been
greatly studied in literature. However, the ability to withstand high power under extreme
conditions and related safe operating area (SOA) concerns in GaN HEMT, including
the failure mechanisms which determine its SOA boundary are still not clearly
understood. This thesis aims to investigate devices under pulse stress conditions, the
scenario which is more realistic to the practical power electronic circuits. Integrated
electrical and mechanical stress characterization routines involving Raman/PL mapping
and CL spectroscopy are used to understand the evolution of failure. SEM and
TEM analysis of damaged regions provided physical insight into the underlying degradation
phenomena. Distinct device behaviour of AlGaN/GaN HEMT is observed in
high current regime with dependence on various design and technology parameters.
Failure power, shows power law-type behaviour. Device degrades in cumulative manner
attributed to deep level traps and the degradation is nicely correlated with the failure
threshold. Increased voltage stress leads to defect generation and increased trap density
in gate-drain region and carrier trapping leads to electric field shift and peaking towards
drain edge. Non-uniform carrier trapping across the device width, triggers avalanche
instability and lowers the SOA boundary. Avalanche instability is absent when carrier
trapping is suppressed with sub-bandgap UV light. Device failed in gate-source region
with carrier trapping and in absence of trapping (with UV exposure), failure occurred
in gate-drain region. Stress accumulation at drain edge creates defects underneath drain
contact. ON-state SOA is limited by tensile stress in the gate-to-drain region. SOA boundary in OFF-state was found to deteriorate due to compressive stress at drain-gate
edge. Furthermore, different techniques are used to compensate for the trap induced
field shift and restore SOA. Field shift can be can be tuned by gate recess depth. At
optimum recess depth, field peaks at gate/drain are suppressed and relatively more
uniform field distribution is achieved and improves SOA. To further improve SOA;
polarization doping is added to AlGaN/GaN HEMT. Nearly a two-fold improvement
in SOA is realized with PSJ. Failure in OFF-state occurs with gate stack degradation
while ON-state failure happens due to hotspot formation at the PSJ edge and is thermally
driven. SOA reliability of GaN HEMT is also be limited by premature failure of
Schottky gate. Robustness of Schottky diodes with recesses and non-recessed anode is
studied. Failure in forward mode is found to be assisted by generation of traps at the
GaN/Schottky interface and Schottky barrier gradually turns Ohmic in nature. Failure
under reverse mode, is observed to be governed by piezoelectric stress distribution in
anode-cathode region. The stress induced trap generation is found to slow down when
UV light is exposed, which is due to fast de-trapping of carrier. During pulse operation,
the SOA of GaN HEMT is observed to shrink with time. Such shift in SOA boundary
is not seen in Si power transistors. To investigate the root cause, devices are realized
on commercially available AlGaN/GaN stack which is qualified for 10-year lifetime
under DC conditions. Surprisingly, the stack fails faster under cyclic pulse transient
stress posing serious limitation to device reliability and SOA. Interestingly, TTF was
found to improve when pulse rise time was increased. In depth investigations are done
using On-the-fly electrical, optical and materials characterization to understand the root
cause. Rapid and more sever changes in device’s RON, ION and VTH are observed under
pulse stress compared to that under DC condition. Drain to substrate vertical leakage
hysteresis is found to increases with stress time PL mapping of drain-source region
reveals increased defect generation introducing deep level traps. Highest PL intensity
is observed near the drain contact. CL depth profiling reveals spatial location of newly
formed defects, in GaN buffer in the drain contact vicinity. Raman map further confirms
mechanical strain builds up at AlGaN transition-region/GaN interface in buffer
region underneath the drain contact. Post failure cross-sectional SEM shows a catastrophic
damage in GaN buffer, in vicinity of drain contact. HR-TEM of defected region
reveals fine cracks near GaN buffer and AlGaN transition interface. However, under
DC stress, damage is localized to device surface and no failure signature is observed in
the bulk. An electrical shock-based fatigue phenomenon is found to be responsible for
time dependent GaN Epi stack failure. A comprehensive failure model is proposed and is experimentally verified | en_US |
