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dc.contributor.advisorParekhji, Rubin
dc.contributor.advisorAmrutur, Bharadwaj
dc.contributor.authorPrasanth, V
dc.date.accessioned2020-06-04T05:36:16Z
dc.date.available2020-06-04T05:36:16Z
dc.date.submitted2020
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/4431
dc.description.abstractIntegrated Circuits (ICs) are used to realize multitude of real life systems. These real life systems have ICs interacting with physical systems (this combination being referred to as cyber-physical systems or hybrid systems) and many of them are used in safety critical applications. The implications of a fault in any of the constituent components of the system must be analysed and appropriately addressed to mitigate its potentially dangerous after effects. Given the increasing dependence on ICs to meet the functional requirements of safety critical applications, safety analysis of ICs plays an important role in ensuring safety of the application performed by the system. Today, safety analysis of ICs used in such systems is typically done in isolation of the end application and associated physical system due to practical considerations like safety analysis complexity, lack of a proper physical system model, etc. Many cyber-physical systems have an acceptable tolerance determined by the application due to the inertial nature of the physical system, error tolerance capability in closed loop applications, built-in hardware and software functionality, etc. These tolerances can be beneficially employed to reduce the hardware overhead required to implement safety. In this work, we investigate the problem of building affordably robust soft-error resilient systems based upon flip-flop protection. We develop methods to identify the minimal set of critical flip-flops which must be protected in an integrated circuit, keeping in mind the inherent tolerances (resiliency) of the system into which it is incorporated.en_US
dc.description.sponsorshipTexas Instrumentsen_US
dc.language.isoen_USen_US
dc.rightsI grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertationen_US
dc.subjectFunctional Safetyen_US
dc.subjectISO26262en_US
dc.subjectSemiconductoren_US
dc.subjectIntegrated Circuiten_US
dc.subjectIEC61508en_US
dc.subjectCyber-Physical Systemsen_US
dc.subject.classificationTechnologyen_US
dc.titleFunctional Safety Analysis Techniques for Integrated Circuits Used in Cyber-Physical Systemsen_US
dc.typeThesisen_US
dc.degree.namePhDen_US
dc.degree.levelDoctoralen_US
dc.degree.grantorIndian Institute of Scienceen_US
dc.degree.disciplineEngineeringen_US


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