| dc.description.abstract | Metal-insulator-metal (MIM) capacitors are used for analog, RF, and DRAM applications in ICs. The International Technology Roadmap for Semiconductors (ITRS) specifies continuing increase in capacitance density (> 7 fF/ m2), lower leakage current density (< 10 8 A/cm2), very low effective oxide thickness (EOT < 1 nm, for DRAM applications), and better capacitance density-voltage (C-V) linearity ( < 100 ppm/V2, for analog/RF applications). In addition, the maximum fabrication/processing temper-ature should not be greater than 400 0C, in order to be compatible with the thermal budget of back-end fabrication steps. Low dielectric constants of conventional SiO2 and Si3N4 capacitors limit the capacitance densities of these devices. Although scaling down of dielectric thickness increases the capacitance density, it results in large leakage current density and poor C-V linearity.
In this work, the effects of high-k materials (Eu2O3, Gd2O3, TiO2) on the device performance of MIM capacitors are studied. The performance of multi-dielectric stack, and doped-dielectric stack devices are also investigated. The effects of anneal temperature, anneal ambient, anneal mode, and dielectric thickness on device performance are evaluated. C-V, current density-voltage (J-V), and reliability measurements are performed to benchmark the electrical performance, and this is correlated to the structural and material properties of the films through ellipsometry, scanning electron microscopy (SEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS) measurements.
High-performance MIM capacitors are fabricated by using (RF sputtered) Eu2O3 dielectric. The fabricated devices are subjected to different anneal conditions, to study their device performance. Forming gas (FG) and argon (Ar) annealed devices are shown to have higher capacitance densities (7 fF/ m2jF G), lower leakage current densities (3.2 10 8 A/cm2jAr at -1 V), and higher , compared to oxygen (O2) annealed de-vices ( 100kHz = 193 ppm/V2jO2). The electrical characterization results are correlated with the surface chemical states of the films through XPS measurements. The annealing ambient is shown to alter the surface chemical states, which, in turn, modulate the electrical characteristics.
High-density MIM capacitors are fabricated by using (RF sputtered) Gd2O3, and Gd2O3-Eu2O3 stacked dielectrics. The fabricated Gd2O3 capacitors are also subjected to different anneal conditions, to study their device performance. Although Gd2O3 capacitors provide high capacitance density (15 fF/ m2), they suffer from high leakage current density, high , and poor reliability. Therefore, stacked dielectrics of Gd2O3 and Eu2O3
(Gd2O3/Eu2O3 and Eu2O3/Gd2O3) are fabricated to reduce leakage current density, improve , and improve reliability, with only a marginal reduction in capacitance density, compared to Gd2O3 capacitors. Density of defects and barrier/trap heights are extracted for the fabricated capacitors, and correlated with the device characteristics.
High-performance MIM capacitors with bilayer dielectric stacks of (ALD-deposited) TiO2-ZrO2, and Si-doped ZrO2 are characterized. Devices with (ALD-deposited) TiO2/ ZrO2/TiO2 (TZT) and AlO-doped TZT stacks are also characterized. The influence of doping on the device performance is studied. The surface chemical states of the deposited films are analyzed by high-resolution XPS. The structural analysis of the samples is performed by XRD measurements, and this is correlated to the electrical characteristics of the devices. Reliability measurements are performed to study the effects of constant voltage and current stress on device performance. High capacitance density (> 45 fF/ m2), low leakage current density (< 5 10 8 A/cm2 at -1 V, for most devices), and sub-nm EOT are achieved. These parameters exceed the ITRS specifications for DRAM storage capacitors. | en_US |
