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    Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models 

    Balssubramanian, Suresh (2011-04-13)

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    Author
    Balssubramanian, Suresh (1)
    SubjectApplication Specific Integrated Circuits (ASIC) (1)Computer Aided Design (1)Digital Signal Processing (DSP) (1)Electronic Engineering (1)Integrated Circuits (1)Phase Frequency Detector (PFD) (1)Phased Locked Loop (1)Phased Locked Loop Design - Behavioral Models (1)PLL Design (1)Voltage Controlled Oscillators (VCO) (1)... View MoreDate Issued2011 (1)Has File(s)Yes (1)

    etd@IISc is a joint service of SERC & J R D Tata Memorial (JRDTML) Library || Powered by DSpace software || DuraSpace
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