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    Process Variability-Aware Performance Modeling In 65 nm CMOS 

    Harish, B P (2011-02-25)
    With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, ...

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    AuthorHarish, B P (1)Subject
    65nm CMOS (1)
    Circuit Delay Distribution (1)Circuit Delay Performance (1)Circuit Design (1)CMOS Designs (1)CMOS Digital Circuits (1)Complementary Metal Oxide Semiconductors (1)
    Electronic Engineering (1)
    Gate Delay Models (1)NAND Gate (1)... View MoreDate Issued2011 (1)Has File(s)Yes (1)

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