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Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation
Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the ...
Low Power Test Methodology For SoCs : Solutions For Peak Power Minimization
Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power ...