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    Power Issues in SoCs : Power Aware DFT Architecture and Power Estimation 

    Tudu, Jaynarayan Thakurdas (2018-01-10)
    Test power, data volume, and test time have been long-standing problems for sequential scan based testing of system-on-chip (SoC) design. The modern SoCs fabricated at lower technology nodes are complex in nature, the ...

    Low Power Test Methodology For SoCs : Solutions For Peak Power Minimization 

    Tudu, Jaynarayan Thakurdas (2013-09-13)
    Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power ...

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    Author
    Tudu, Jaynarayan Thakurdas (2)
    Subject
    Computer Science (2)
    VLSI Testing (2)Aware Scan Architecture (1)BILP Programming (1)Capture Power (1)Capture Power Reduction (1)Congestion Aware Scan Architecture (1)Design-for-Test (DFT) Architecture (1)Electric Power (1)Electric Power Minimization (1)... View MoreDate Issued2013 (1)2018 (1)Has File(s)Yes (2)

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