Browsing Division of Electrical, Electronics, and Computer Science (EECS) by Subject "Bank Level Parallelism (BLP)"
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Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures
Integrated Heterogeneous System (IHS) processors pack throughput-oriented GPGPUs along-side latency-oriented CPUs on the same die sharing certain resources, e.g., shared last level cache, network-on-chip (NoC), and the ...