Browsing Division of Electrical, Electronics, and Computer Science (EECS) by Advisor "Govindarajan, R"
Now showing items 1-9 of 9
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2-Level Page Tables (2-LPT): A Building Block for Efficient Address Translation in Virtualized Environments
Efficient address translation mechanisms are gaining more and more attention as the virtual address range of the processors keeps expanding and the demand for machine virtualization increases with cloud and data center-based ... -
Compiler Transformations For Improving The Performance Of Software Transactional Memory
(2013-03-27)Expressing synchronization using traditional lock based primitives has been found to be both error-prone and restrictive. Hence there has been considerable research work to develop scalable and programmer-friendly alternatives ... -
Efficient Compilation Of Stream Programs Onto Multi-cores With Accelerators
(2010-12-30)Over the past two decades, microprocessor manufacturers have typically relied on wider issue widths and deeper pipelines to obtain performance improvements for single threaded applications. However, in the recent years, ... -
Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures
Integrated Heterogeneous System (IHS) processors pack throughput-oriented GPGPUs along-side latency-oriented CPUs on the same die sharing certain resources, e.g., shared last level cache, network-on-chip (NoC), and the ... -
Improving Last-Level Cache Performance in Single and Multi-Core Processsors
(2018-04-23)With off-chip memory access taking 100's of processor cycles, getting data to the processor in a timely fashion remains one of the key performance bottlenecks in current systems. With increasing core counts, this problem ... -
Performance Characterization and Optimizations of Traditional ML Applications
Even in the era of Deep Learning based methods, traditional machine learning methods with large data sets continue to attract significant attention. However, we find an apparent lack of a detailed performance characterization ... -
Scaling Context-Sensitive Points-To Analysis
(2014-05-06)Pointer analysis is one of the key static analyses during compilation. The efficiency of several compiler optimizations and transformations depends directly on the scalability and precision of the underlying pointer analysis. ... -
Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques
(2009-05-19)Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level ...