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Statistical Modeling Of Transistor Mismatch Effects In 100nm CMOS Devices

dc.contributor.advisorBhat, Navakanta
dc.contributor.authorSrinivasaiah, H C
dc.date.accessioned2011-05-16T05:05:02Z
dc.date.accessioned2018-07-31T04:50:54Z
dc.date.available2011-05-16T05:05:02Z
dc.date.available2018-07-31T04:50:54Z
dc.date.issued2011-05-16
dc.date.submitted2004
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/1202
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/1563/G18591-Abs.pdfen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG18591en_US
dc.subjectComplimentary Metal Oxide Semiconductor Devicesen_US
dc.subjectCMOS Devicesen_US
dc.subjectTransistor Mismatchen_US
dc.subject.classificationElectronic Engineeringen_US
dc.titleStatistical Modeling Of Transistor Mismatch Effects In 100nm CMOS Devicesen_US
dc.typeThesisen_US
dc.degree.namePhDen_US
dc.degree.levelDoctoralen_US
dc.degree.disciplineFaculty of Engineeringen_US


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