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Statistical Design For Yield And Variability Optimization Of Analog Integrated Circuits

dc.contributor.advisorShiva Prasad, A P
dc.contributor.authorNalluri, Suresh Babu
dc.date.accessioned2011-05-13T10:21:22Z
dc.date.accessioned2018-07-31T04:50:34Z
dc.date.available2011-05-13T10:21:22Z
dc.date.available2018-07-31T04:50:34Z
dc.date.issued2011-05-13
dc.date.submitted2004
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/1198
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/1558/G18903-Abs.pdfen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG18903en_US
dc.subjectIntegrated Circuits - Design and Constructionen_US
dc.subjectAnalog Integrated Circuit Designen_US
dc.subjectStatistical MOS Model (SMOS)en_US
dc.subjectResponse Surface Methodology (RSM)en_US
dc.subjectStatistical Simulationen_US
dc.subject.classificationElectronic Engineeringen_US
dc.titleStatistical Design For Yield And Variability Optimization Of Analog Integrated Circuitsen_US
dc.typeThesisen_US
dc.degree.nameMSc Enggen_US
dc.degree.levelMastersen_US
dc.degree.disciplineFaculty of Engineeringen_US


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