Electrical Communication Engineering (ECE)

0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology

0.5V Subthreshold Region Operated Ultra Low Power Passive Sigma Delta ADC in 180 NM CMOS Technology Satyadev, Singh Kamlesh With increasing demand of IoT devices, medical devices, remote sensors; the design of low power analog interface is becoming focus. Generally, for low frequency applications the Sigma Delta ADCs are used due to their very good resolution capability for such interfaces. Hence extensive work is being done to design ultra-low power Sigma Delta ADC. Most of the work has been done on optimizing loop filter design both in terms of architecture and its basic building element, op-amps. Recently, one of the prime focus of such research is Passive Sigma Delta ADC, where the loop filter is implemented with passive elements instead of active elements like op-amp. In this work, a subthreshold region operated Passive Sigma Delta design has been explored. The thesis discusses a different analytical approach to analyze passive SDM ADC than the usual circuit level analysis used traditionally. The Simulink modeling of a passive SDM ADC was addressed to study block level performance. The circuit level implementation was carried out in Cadence environment. Both pre-and-post layout level simulations were conducted. The passive SDM ADC designed in this work has a Sampling frequency of 10MHz, with a signal BW of 10KHz. An ENOB of 10.4 bits is achieved at power dissipation of only 4μW. The proposed ADC has very competitive FOM (Figure of Merit) in comparison with published literature.

A digital correlation receiver for the Gauribidanur Decametre wave radio telescope

A digital correlation receiver for the Gauribidanur Decametre wave radio telescope Ravindra, D K A low-frequency radio telescope operating at 34.5 MHz has been set up at Gauribidanur (Latitude: 13°36′12″ N, Longitude: 77°26′07″ E) in the form of a T-shaped array antenna. It consists of: A 1.38 kilometre long array of 160 elements along the East–West line. A 90-element array extending southward from the centre of the East–West array. When the output of the East–West array is correlated with that of the North–South array, a beam of 26′ in right ascension and 38′ in declination is produced. The telescope is a meridian transit instrument with the capability for tilting the beam in the meridian. Digital Correlation Receiver System To take advantage of the aperture synthesis technique in mapping large regions of the sky in a single scan, a Digital Correlation Receiver System has been designed, constructed, and incorporated into the above-mentioned instrument. In this system: The output of the East–West array is simultaneously correlated with each of the 90 spatial frequency components of the sky brightness distribution corresponding to the spacings of the North–South elements from the East–West array. A brightness distribution map for various zenith angles can then be computed by taking the inverse Fourier transform of the measured correlation coefficients. Hardware and Processing A fast, on-line, hardware Fourier Transform (FT) processor has been designed and constructed. The Digital Correlation Receiver System provides: Delay and phase corrections Weighting of the correlation coefficients on an on-line basis A microcomputer has been designed and constructed for use as a peripheral controller to: Acquire the data from the FT processor Display the brightness distribution map on a video monitor Record the data on magnetic tape for further processing Field Trials The Digital Correlation Receiver System has been tested by carrying out field trials, and the results are presented.

A simplified approach for wordlength reduction of control memory of microprogrammed processors

A simplified approach for wordlength reduction of control memory of microprogrammed processors Mitra, Nidrita Since its inception by Wilkes in 1951, microprogramming has made considerable progress in both techniques and applications. Much of this progress has been made possible by significant improvements in memory technology. Advances in memory technology have resulted in the availability of large, fast, and economical stores from which microprograms can be accessed rapidly. Furthermore, the ability to alter the contents of the control store has renewed interest in interpreters and in high-level language architectures. With the emergence and development of Very Large Scale Integration (VLSI) technology, the general expectation is that microprogramming will play an even larger role in the implementation of complex single-chip processors, largely because of the regularity of the microprogrammed control unit structure. This regularity is not only conducive to the efficient utilization of silicon real estate but is also effective in reducing design time, easing the problem of testing and debugging integrated circuits, and promoting the use of design automation for generating circuit-level designs. Furthermore, in order to enhance system performance, functionality, reliability, and security, many heavily used functions and applications that were previously implemented in software are being migrated into firmware. This leads to much larger and more complex microprograms than were encountered in the past. Abstract As microprogramming is gathering more importance in computer system design, much attention has been paid to the economic aspect of the microprogrammed control store. In a microprogrammed processor, the size of the control memory depends upon the length (in bits) of the control store word. The word-length reduction techniques attempt to reduce the number of bits in each control store word. As a result, the control store size is reduced. Several methods exist for word-length reduction: The earliest methods are simple, using obvious techniques such as function extraction. Later formal techniques employ the notions of covering, where classical switching theory is applied. In all procedures, word-length reduction methods assume that the structure of each microinstruction in terms of various microoperations has already been decided upon in such a way that the parallelism among the microoperations is maintained. Each of the microinstructions so constituted becomes a word of the microprogrammed control memory. Contribution of the Thesis In this thesis, a new method of reducing the word-length of a microprogrammed control store has been presented. The method is based on a simple and systematic approach, wherein the computation of a limited number of maximal compatibility classes of a subset of microoperations is required. The algorithm is fast and generates minimal solutions in every case.

A token ring local area network for small systems application

A token ring local area network for small systems application Mustaq Ali, V This research work deals with a new design/ and study of a token ring local area network (LAN) for small systems application like microcomputer network. The salient features of the work carried out are as follows: “ Development of a new access technique and a distributed algorithm to realize a token ring/ “ hardware design and construction of a microprocessor based Ring Interface Unit and an experimental ring net, - construction of a traffic-adaptive simulation model with a cyclic queuing procedure for performance evaluation/ and - study of a multiple token ring which is modelled as separate single rings with a mixed class of stations. Many access techniques have been developed to satisfy the requirements of a local area network/ but the token ring has turned out to be the most suitable scheme for different applications ranging from office automation to real-time systems like process control. Numerous comparative analyses have proved the performance superiority of the token ring over the other schemes. The analysis has also shown the robustness of the token ring to the large variation in the network parameter and traffic. Elowever/ as far as small systems applications are concerned/ the realization of a token ring becomes quite complex in its control procedure/ and relatively expensive mainly due to lack of an LSI implementation of this access scheme. In this work/ a new and simple approach is described for designing and implementing an inexpensive token ring system. Also/ modelling and performance studies of the ring net are done in a more realistic small systems environment. Initially/ in order to find a cost-effective approach to construct a ring node, standard Data Link protocols that are readily available in the form of low-cost single chip hardware are surveyed. As a result/ the IBM-SDLC loop protocol is found to be suitable due to the resemblance of its architecture with the token ring. However/ in the SDLC loop architecture/ the procedure of having a permanent primary station to control the entire loop generates an unbalanced traffic in the network; and poses reliability problems if the primary station fails. These are unsuitable features for a multi-user system like LAN. Therefore/ to avoid these difficulties, in this work/ all the SDLC stations are given an equal priority to control the loop- This is done by suitably modifying the SDLC frame format and the polling procedure. In accordance with these modifications/ a distributed algorithm is developed to convert the centralized SDLC loop architecture into a decentralized network like that of token ring. This algorithm allows the role of the primary station to circulate among all the stations in the loop. That is, it permits any station to acquire this primary status when it has a message to transmit. After the loop-transmit/ the transmitting station is made to pass its primary status to the next access seeking station/ and thus making the loop control become distributed. To realize a loop station/ an INTEL 8085 microprocessor based Ring Interface Unit is constructed and it is tested in an experimental ring net. The network-control part of the system includes a protocol controller/ a DMA controller/ a transceive buffer, a clock recovery and a bypass circuits/ and network command and control software. Although there exist numerous performance analyses on token ring, analyses pertaining to the study of the system in a realistic environment are scarce. In this work, a more general and versatile computer simulation model with a cyclic queueing procedure is constructed. In this model, it is observed that working with a single model (explicit OR implicit polling type) to operate a wide range (0.1 to >0.9) of network traffic is inefficient. For instance, in the case of a low message arrival rate (<0.5), the execution time of the simulation program (of explicit polling) becomes prohibitively high. Because, a light traffic in the ring induces the circulation of idle-token for most of the time: a system state that does not contribute to the servicing of a message. Therefore, in order to improve the program's runtime efficiency, the model is broken into two .different types - low traffic and high traffic models. Depending on the computational time of the previous run, the proper model is switched on for further simulation in the other ranges of traffic. This "traffic-adaptive" simulation model reduces the overall CPU-time of the program for all ranges of traffic. Attempts are made to verify this simulation model by comparing it with known analytical results, and the results are found to be satisfactory. Apart from this varying traffic model, a saturated load (continuously queued) model is also developed. This aims to analyse the sensitivity of the token ring at extreme operational conditions. The simulaton work is largely directed towards the modelling of the ring net in a more realistic small systems environment, i.e., where the network is connected with a mixed class of stations like work-station/ file-server/ and bridge. This unbalanced traffic model is used to analyse multiple rings (2- rings) which are connected by a bridge. The flow of message between rings is characterized by an *'interaction-probability" with which a ring net transfers its messages to the other. This parameter is used to calculate the arrival rate of messages at a bridge-station of the ring net, and the multiple ring net is then modelled as logically separated single rings which have an unbalanced traffic in the net due to the presence of a bridge station. While doing so, the delay history of the messages that arrive at the bridge-station from the other ring is properly accounted for. The above analyses are mainly used to address the problems and to device effective solutions to cope with the natural growth of stations in a ring net of a small systems environment. From different analyses^ it appears that configuring a large single ring net into multiple rings connected by a bridge is a better choice than altering the existing capacity of the growing ring. Besidesf in order to improve the throughput-delay efficiency of the multiple ring net, performance studies for various ringinteraction- probablities are done. The different techniques applied in this effort are: a) giving a "priority-servicing" at the bridge-station/ and b) applying a "resource-balancing" approach in the ring nets to reduce the flow of many messages accross the bridge.