Browsing by Advisor "Singh, Virendra"
Now showing items 1-4 of 4
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Efficient Fault Tolerance In Chip Multiprocessors Using Critical Value Forwarding
(2013-09-03)Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to transient faults, wear-out related permanent faults and process variations. Decreasing CMOS reliability implies that ... -
Low Overhead Soft Error Mitigation Methodologies
(2018-03-06)CMOS technology scaling is bringing new challenges to the designers in the form of new failure modes. The challenges include long term reliability failures and particle strike induced random failures. Studies have shown ... -
Low Power Test Methodology For SoCs : Solutions For Peak Power Minimization
(2013-09-13)Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power ... -
Memory Efficient Regular Expression Pattern Matching Architecture For Network Intrusion Detection Systems
(2014-06-05)The rampant growth of the Internet has been coupled with an equivalent growth in cyber crime over the Internet. With our increased reliance on the Internet for commerce, social networking, information acquisition, and ...