Browsing by Advisor "Govindarajan, R"
Now showing items 21-22 of 22
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Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques
(2009-05-19)Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level ... -
A Systematic Approach To Synthesis Of Verification Test-Suites For Modular SoC Designs
(2009-03-03)SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the ...