| dc.description.abstract | Colloidally produced nanocrystals (NCs) arranged in thin films hold promise for next-generation semiconductors. These NCs offer tunability in semiconductor properties due to their size, shape, composition, and surface characteristics. However, the performance of NC-based optoelectronic devices still lags behind theoretical predictions. This is primarily attributed to electronic deep-level trap states, which act as recombination centres and limit effective mobility. The large surface area, hybrid nature, and disordered structure of NCs contribute to the abundance of trap states. To improve device performance, it is crucial to identify these defects and understand their impact on electrical characteristics. This work employs Deep Level Transient Spectroscopy (DLTS) to identify deep-level defects in NCs and NC-based photovoltaic devices. DLTS allows for determining defect level energy, concentration, capture cross-section, and differentiation between minority and majority carrier traps. This technique is highly sensitive, capable of detecting low defect concentrations, and resolves signals from various traps.
The conventional DLTS system suffers from drawbacks, including the need for multiple temperature cycles, which can lead to poor device contact and thin film adhesion. Additionally, maintaining a consistent temperature environment for each measurement is challenging, resulting in low-quality data. To address these issues, we develop a microcontroller-based DLTS system. This system utilizes a capacitance meter and electronic circuits controlled by an Arduino-Due microcontroller. We have used Arduino-Due to generate the filling pulse, monitor the capacitance, temperature, data acquisition, timing control and signal processing. By conducting measurements within a single temperature scan, our system saves time, improves accuracy, and reduces experimental failures. We validate the innovative instrumentation using a gold-doped silicon p-n junction sample. Furthermore, we apply this microcontroller-based DLTS system to study deep-level defects in Mercury Telluride (HgTe) nanocrystal-based photovoltaic devices.
We fabricate photovoltaic devices based on HgTe NCs/TiO2 and employ capacitance-voltage (C-V) and DLTS techniques to investigate and collect quantitative data on deep-level trap states. DLTS confirms the presence of interface trap states, while frequency-dependent capacitance measurements support the influence of charge storage in these nanocrystal-based heterostructures, offering insights for advanced device development. Using DLTS, we measure trap energy, capture cross-section, and concentration. These traps in the photovoltaic devices can act as recombination centres and effectively interact with valence and conduction bands. Poor device responsiveness is observed in the ITO/TiO2/HgTe/Au configuration due to inefficient photo charge extraction.
To enhance device performance, we optimize hole and electron extractions by introducing a Molybdenum Oxide (MoO3) hole extraction layer. We investigate the effect of this contact layer on trap level formation in the FTO/TiO2/HgTe/MoO3/Au photovoltaic device using low-temperature I-V, C-V, C-F, and microcontroller-based DLTS measurements. The obtained trap energy levels are comparable to those of the ITO/TiO2/HgTe/Au device, indicating the presence of trap levels at the TiO2/HgTe interface and no significant impact of the MoO3 contact layer on trap formation. Our microcontroller-based DLTS system proves to be an efficient tool for determining defect levels in heterojunctions based on nanocrystals. Surface states at the HgTe nanocrystals and oxygen vacancies in TiO2 are identified as the main contributors to trap levels, primarily located at the TiO2/HgTe interface. To further confirm the origin of trap states, we fabricate an ITO/HgTe/Al Schottky junction and measure the defect level energy using low-temperature I-V and C-F measurements. The obtained energy values support trap levels resulting from surface reconstruction at the TiO2/HgTe heterojunction interface. Passivating these trap states is crucial for improving device effectiveness. | en_US |
