| dc.description.abstract | Multilevel voltage source inverter transformed conversion of DC to AC for medium to high power application. With increasing electric power demand, the multilevel converter allows high power density converters for medium to high voltage high power applications. Motor drives, high voltage DC (HVDC) transmission, renewable energy systems, and electric traction are some applications that employ multilevel converters. Conventional two-level inverters need to switch between full DC link to ground potential and require voltage blocking equal to the supply voltage. In addition, 2-level inverters require harmonic filters for filtering harmonics in the output voltage. The filters are costly and bulky and dissipate power, decreasing the system's overall efficiency. Multilevel inverters overcome the disadvantages of conventional inverters by switching intermediate voltage levels between DC link voltage and zero voltage. The higher resolution in the inverter voltage levels reduces the output voltage error compared to the required sinusoidal waveform and improves the harmonic quality. The converter's switching frequency is reduced to minimise the switching losses, thereby increasing the system efficiency. The dv/dt of the multilevel converter is less, which reduces the switching stress on the device and brings down the conductive and radiative emissions. Multilevel inverters can also utilise time-tested low voltage semiconductor technologies to build the converters, improving the system's reliability and easy component availability. Basic and most popular multilevel topologies are cascaded H-bridge inverter, neutral point clamped inverter and flying capacitor inverter. Another class of hybrid multilevel inverters is obtained by cascading basic multilevel inverter cells, which can generate high-quality output voltage waveforms with greater voltage levels. Hybrid multilevel inverters for induction motor drives are also obtained by configuring the motor as an open-end and feeding on both sides of the induction motor.
The conventional voltage source inverter generates a hexagonal space vector structure. The inverters are required to operate in the overmodulation region for maximum utilisation of the available DC-link. Operating in the overmodulation region generates lower-order harmonics in the phase voltage and causes several undesirable problems in the systems. The linear modulation range of the hexagonal space vector structure is 90.7\% of the peak fundamental voltage for the maximum modulation index. Induction motor drives using hexagonal space vector structure suffer from torque pulsations on the motor shaft, which could even lead to total system failure. The harmonics in the system affect the dynamic performance of closed-loop current control of the motor and generate significant power loss.
Various techniques have been proposed in the literature to suppress the problems caused by harmonics. Increasing the switching frequency of the converter is one such method to reduce the effect of harmonics by having lowest harmonics only at switching frequency, which is easy to filter out. High switching frequency is not a practical solution for medium and high power applications due to the high magnitude of switching loss in the device, resulting in worse electromagnetic compatibility performance. Also, the increased switching frequency is only effective for operation within the linear modulation range. Another conventional method for harmonic suppression is using passive filters. But, for variable frequency operation like in induction motor drives, filtering out lower order harmonics requires bulky filters, which increases the system's size and cost and adds to the resistive loss. Moreover, the addition of the filter to the system affects the system's dynamic performance and reduces the fundamental voltage at the output. Selective harmonic elimination (SHE) is a special pulse width modulation (PWM) to suppress the harmonics by introducing fixed notches in the output. SHE operates with a low switching frequency but suffers from low DC-link utilisation due to the introduction of the notches. Also, the method becomes complex for the elimination of multiple harmonics and has poor dynamic performance. An elegant method to eliminate harmonics in the output voltage is to realise space vector structures with inherent harmonic elimination.
Polygonal space vector structure with a higher number of sides than a hexagon, such as 12-sided polygon and 18-sided polygon, eliminates lower order harmonics. 12-sided polygon eliminates the lower order harmonics of the order 5th and 7th and has harmonics only from 11th and 13th. 18-sided polygon eliminates the harmonics up to the 13th order and only harmonics from the 17th and 19th order. The polygons with a higher number of sides are closer to a circle geometrically and have an increased linear modulation region than hexagon (6-sided) for a given DC-link voltage. Generating higher fundamental voltage inverter operations compare to hexagon for the same DC-link voltage leads to better DC-link utilisation. Schemes generating multilevel polygonal space vector structures have evolved to incorporate the advantages of multilevel converters. There are several challenges to generating multilevel polygonal structures, including the requirement of large capacitance, the complexity of PWM techniques etc. Power circuit topologies with a single DC source to generate polygonal space vector structures have evolved but suffer from the requirement of large capacitor size. This thesis proposes a capacitor size reduction methodology and a simple PWM strategy for multilevel polygonal space vector structure. Chapter 1 introduces various harmonic suppression schemes and topologies for generating multilevel inverter polygonal space vector structures.
A multilevel 12-sided polygonal voltage space vector generation scheme for variable-speed drive applications with a single DC-link operation requires an enormous capacitance value for cascaded H-bridge (CHB) filters when operated at lower speeds. The multilevel 12-sided polygonal structure is obtained in existing schemes by cascading a flying capacitor inverter with a CHB. Chapter 2 proposes a new scheme to minimise the capacitance requirement for full-speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimise the selection of vector redundancies among the CHBs to minimise the floating capacitors' voltage ripple. The algorithm computes the optimal vector redundancies by considering the instantaneous capacitor voltages and the phase currents.
Chapter 3 proposes a simple unified pulse width modulation (PWM) strategy for multilevel polygonal space vector structure (SVS) partitioned into symmetric triangles for the first time. The algorithm obtains the PWM timing durations for a 2-level polygonal voltage SVS in a sampling duration using only the sampled reference values of voltages. The PWM timings obtained for a 2-level structure are then mapped to multilevel SVS. The matrices used for this mapping remain the same irrespective of the sides of the polygon. The smallest triangle encompassing the reference voltage vector in the multilevel structure is identified using this algorithm along with the PWM timings for which the voltage vectors forming the vertices of this smallest triangle are applied. The algorithm involves only operations like addition, multiplication, and logical comparisons. A general implementation scheme for an N-level, p-sided polygon is presented in this paper. A novel 5-level 18-sided SVS is also proposed in this paper. The scheme incorporates the advantages of harmonic elimination due to an 18-sided polygon and the inherent advantages of a multilevel inverter.
A multilevel variable speed induction motor drive scheme using an 18-sided polygon with a very dense voltage space vector structure (SVS) is proposed in chapter 4. The proposed SVS consists of 101 concentric layers of 18-sided polygons. The 18-sided polygonal SVS eliminates lower order harmonics 5th, 7th, 11th and 13th orders from the output voltage for the entire modulation range. The linear modulation range of the 18-sided polygon is extended to 99\% of the base speed compared to 90.7\% of the hexagonal SVS. It also has higher peak phase fundamental voltage at the output and better DC-link utilisation than conventional inverters. The SVS is generated by superposition of 5-level main hexagonal SVS of radius VDC and 5-level auxiliary hexagonal SVS of radius 0.379VDC. The dense voltage space vector structure facilitates the generation of reference by nearest vector switching in the 18-sided polygon, reducing the semiconductor devices' switching. The vector switched to realise the reference voltage in a sampling period is only one polygonal vector throughout the modulation range, drastically reducing switching loss and electromagnetic emissions.
Simulation and experimental results of the proposed drive scheme are presented to prove the effectiveness of the drive scheme. The inverter is modelled and extensively simulated using a MATLAB-SIMULINK environment. An experimental setup using inverter modules is set up to test the inverter. The semiconductor switches used are SKM75GB12T4 and IRF260N. Gate drive circuits based on opto-isolated IC M5792L from Mitsubishi and capacitive isolated IC ISO5451 from Texas Instruments are used. TMS320F28335 DSP from Texas Instruments and XC2S200 FPGA from Xilinx were used as the controllers for realising the hardware prototype. A 3-phase open-end induction motor of ratings 15 kW, 415 V, and 4-pole is used for testing the proposed drive schemes. | en_US |
