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dc.contributor.advisorBhat, Navakanta
dc.contributor.authorBhattacharjee, Shubhadeep
dc.date.accessioned2019-08-13T11:27:14Z
dc.date.available2019-08-13T11:27:14Z
dc.date.submitted2018
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/4268
dc.description.abstractThe shrinking of the field-effect transistor (FET), commonly termed CMOS scaling, has revolutionised the semiconductor industry and impacted most aspects of human life. However, this decades-long successful trend of scaling the FET is now facing serious fundamental and technological challenges resulting in diminishing economic returns. The first challenge is that, as device dimensions shrink, electric fields in close proximity start to interfere with each other and disrupt the transistor’s operations. This phenomenon is called the short channel effect (SCE). Second, concurrent (quadratic) reduction in power consumption, an important aspect of scaling, is not possible because of the inability to reduce supply voltage below 1 V. This is primarily because the fundamental nature of charge transport governed by Boltzmann’s statistics restricts the sub-threshold swing (SS, abruptness between OFF to ON transitions) of FETs to the thermionic limit of 60 mV/dec at room temperature. Hence, as we cram in more transistors into the same footprint, energy dissipation and heat management have become fundamental bottlenecks. Clearly, the road ahead needs breakthroughs in new materials and device design. In this thesis, we attempt to tackle both these challenges (SCE and power consumption) by developing high performance, sub-thermionic (SS<60 mV/dec) transistors on 2D semiconductors. Excellent electrostatics inherent to 2D semiconductors make them promising candidates for mitigating SCE, with recent demonstrations of sub-10 nm channel length molybdenum disulphide (MoS2) FETs. However, the development of sub-thermionic transistors on 2D semiconductors has been stymied by inefficient contacts, doping and dielectric integration, which motivates the initial portion of this work. First, we demonstrate how a facile sulfur-based solution can be employed to engineer surface states between MoS2/metal contacts, resulting in substantial reduction in Schottky barrier height. This enables record performance due to a ~6x/10x (Ni/Pd) reduction in contact resistance, along with complete mitigation in contact variability. In addition, through an empirical model we can predict the intrinsic limit of contact resistance in multilayer TMDs. Second, we develop an air-stable, area-selective, CMOS-compatible counterdoping strategy through vacancy engineering, enabling p-FETs and in-plane p/n junction photodioides. Third, we lay a two-part focus on dielectrics. In the first part, we examine the interplay of different scattering mechanisms in 2D charge transport and demonstrate ‘ideal’ nitride dielectric environments for large performance gains (field-effect mobility ~ 73 cm2V-1s-1). In the second part, we Page | VII break the paradigm of atomic layer deposition and employ functionalisation-free e-beam evaporated top gate high-κ HfO2 to achieve near-perfect SS~60 mV/dec operation. Finally, leveraging on the insights from the previous sections, we demonstrate, for the first time, sub-thermionic transport through tunable Schottky contacts in dual gated MoS2 FETs. Two device configurations, the GT3FET and DVATFET, are expounded. The GT3FET has the flexibility to operate either in the sub-thermionic tunnel regime, yielding steep SS<60 mV/dec OR thermionic high mobility regime. Combining the best of both tunnelling and thermionic regimes in the same operation cycle, the DVATFET, the closest to an ‘ideal transistor’, registers SS~29 mV/dec (3 dec) AND high mobility (100 cm2V-1s-1). This work is envisioned to pave a new path in the development of sub-thermionic, high performance FETs operating in the sub-0.5 V ‘green computing’ regime.en_US
dc.description.sponsorshipMeiTY Visvesvariaya PhD Fellowshipen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG28781;
dc.rightsI grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertationen_US
dc.subjectElectronic Devicesen_US
dc.subjectDevice Physicsen_US
dc.subjectField Effect Transistorsen_US
dc.subjectTunnel FETsen_US
dc.subjectField-effect Transistor (FET)en_US
dc.subjectMoS2en_US
dc.subjectDielectricsen_US
dc.subjectVacancy Engineeringen_US
dc.subject2D Semiconductorsen_US
dc.subject.classificationElectronics and Electrical Engineeringen_US
dc.titleMaterials, Processes and Device Design for High Performance, Sub-thermionic MoS2 FETsen_US
dc.typeThesisen_US
dc.degree.namePhDen_US
dc.degree.levelDoctoralen_US
dc.degree.grantorIndian Institute of Scienceen_US
dc.degree.disciplineEngineeringen_US


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