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dc.contributor.advisorBanerjee, Gaurab
dc.contributor.authorLenka, Manas Kumar
dc.date.accessioned2018-10-30T10:16:31Z
dc.date.available2018-10-30T10:16:31Z
dc.date.submitted2018-03-01
dc.identifier.urihttp://etd.iisc.ac.in/handle/2005/4127
dc.description.abstractThe ever growing demand for higher data rates and the heavy usage of wireless communication devices have created frequency congestion on certain bands of the radio spectrum. The push has been towards new standards that can quench this thirst for data capacity and more space on the spectrum. This has led to added complexity and cost for radio platforms. In particular, the increase in the number of antennas, switch banks and pre-select filters have made it challenging to implement these platforms cost-effectively. Therefore, concepts such as software-defined radio(SDR) and cognitive radio(CR) have been proposed to tackle this problem. These concepts, allow the use of a single wideband receiver which can handle multiple radio standards spread across the entire spectrum of interest. The introduction of a common flexible hardware platform eliminates the use of multiple off-chip RF pre-filters and thus lowers cost, reduces complexity and form factor. While attractive, these future radio receivers pose a number of unique challenges to the designer. This thesis focuses on frequency translation (FT) techniques and addresses two key SDR/CR challenges: the robustness to out-of-band interference (OBI) or block-ers and the compatibility with CMOS scaling and system-on-chip (SoC) integration. The thesis studies the principles and the performance limitations of existing FT tech-niques and proposes new circuit-and-system techniques to improve the performance of wideband receivers suitable for SDR and CR applications. First, the performance of the frequency translational resistive feedback receiver frontend is studied and analyzed. Instead of using a conventional LNA, the job of the LNA is shared along the receiver chain through the utilization of frequency translation techniques. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. Though frequency translation is at the core of the receiver functionality, it is accomplished using time-varying, strongly nonlinear passive mixer circuits. So the operation and noise performance cannot be understood using standard LTI circuit analysis techniques. To this end, an in-depth LTV analysis is presented which accurately captures the gain, input matching and the noise performance of the receiver. Next, a wideband blocker tolerant receiver with an RF frequency range of 0.1 GHz to 2.2 GHz is proposed. By using frequency-translational resistive shunt-feedback, the receiver achieves frequency selective input match across its entire range of operation. Four techniques for improving blocker tolerance of the receiver have been utilized: 1) voltage amplification only after baseband filtering 2) blocker rejection at the antenna interface using an N-path filter 3) blocker current cancellation in the baseband 4) frequency translational noise cancellation which uses an auxiliary path to cancel the noise of the main path. By introducing an auxiliary path, the value of the RF transconductor in the main path is halved which in turn relaxes the requirements of the main path and further improves the overall linearity of the receiver while degradation in the noise figure is prevented due to noise-cancellation. As a proof of concept, a receiver prototype is fabricated in a 130 nm CMOS process. The measurement results demonstrate that the receiver achieves +2dBm in-band IIP3 and +27dBm out-of-band IIP3. The measured noise figure varies from 2.6 dB at low frequencies to 3.2 dB at 2.2 GHz. The receiver can tolerate a +2.5 dBm blocker beyond a 40 MHz offset while achieving a blocker noise figure of 4.6 dB for a 0-dBm blocker at 40 MHz offset. Finally, architecture and circuit techniques are proposed to improve the receiver’s resilience to strong harmonic blockers. Designed in a 40nm standard CMOS process, the receiver can tolerate up to -1 dBm harmonic blockers. On the other hand, it achieves a 1-dB standard blocker compression point of +3 dBm and OB-IIP3 of +24 dBm at a 40 MHz offset from the LO frequency.en_US
dc.description.sponsorshipDepartment of Electronics and Information Technology, Govt. of India.en_US
dc.language.isoen_USen_US
dc.relation.ispartofseries;G28720
dc.rightsI grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertationen_US
dc.subjectBlockers - Reciprocal Mixingen_US
dc.subjectFrequency translation techniquesen_US
dc.subjectBlocker Tolerant Receiveren_US
dc.subjectWide-band Input Matchingen_US
dc.subjectBlockers - Harmonic Mixingen_US
dc.subject.classificationResearch Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electronicsen_US
dc.titleBlocker-tolerant Receiver Design Suitable for Software-defined and Cognitive Radio Applicationsen_US
dc.typeThesisen_US
dc.degree.namePhDen_US
dc.degree.levelDoctoralen_US
dc.degree.grantorIndian Institute of Scienceen_US
dc.degree.disciplineEngineeringen_US


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