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dc.contributor.advisorPatnaik, L M
dc.contributor.authorKumar, Mohan J
dc.date.accessioned2005-02-09T04:35:28Z
dc.date.accessioned2018-07-31T07:08:13Z
dc.date.available2005-02-09T04:35:28Z
dc.date.available2018-07-31T07:08:13Z
dc.date.issued2005-02-09T04:35:28Z
dc.date.submitted1992
dc.identifier.urihttp://etd.iisc.ac.in/handle/2005/3925
dc.identifier.srnonull
dc.description.abstractThis thesis, presents a multiprocessor topology, the hierarchical network of hyper-cubes, which has a low diameter, low degree of connectivity and yet exhibits hypercube like versatile characteristics. The hierarchical network of hyper-cubes consists of k-cubes interconnected in two or more hierarchical levels. The network has a hierarchical, expansive, recursive structure with a constant pre-defined building block. The basic building block of the hierarchical network of hyper-cubes comprises of a k-cube of processor elements and a network controller. The hierarchical network of hyper-cubes retains the positive features of the k-cube at different levels of hierarchy and has been found to perform better than the binary hypercube in executing a variety of application problems. The ASCEND/DESCEND class of algorithms can be executed in O(log2 N) parallel steps (N is the number of data elements) on a hierarchical network of hypercubes with N processor elements. A description of the topology of the hierarchical network of hypercubes is presented and its architectural potential in terms of fault-tolerant message routing, executing a class of highly parallel algorithms, and in simulating artificial neural networks is analyzed. Further, the proposed topology is found to be very efficient in executing multinode broadcast and total exchange algorithms. We subsequently, propose an improvisation of the network to counter faults, and explore implementation of artificial neural networks to demonstrate efficient implementation of application problems on the network. The fault-tolerant capabilities of the hierarchical network of hypercubes with two network controllers per k-cube of processor elements are comparable to those of the hypercube and the folded hypercube. We also discuss various issues related to the suitability of multiprocessor architectures for simulating neural networks. Performance analysis of ring, hypercube, mesh and hierarchical network of hypercubes for simulating artificial neural networks is presented. Our studies reveal that the performance of the hierarchical network of hypercubes is better than those of ring, mesh, hypernet and hypercube topologies in implementing artificial neural networks. Design and implementation aspects of hierarchical network of hypercubes based on two schemes, viz., dual-ported RAM communication, and transputers are also presented. Results of simulation studies for robotic applications using neural network paradigms on the transputer-based hierarchical network of hypercubes reveal that the proposed network can produce fast response times of the order of hundred microseconds.en
dc.format.extent4390515 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.publisherIndian Institute of Scienceen
dc.rightsI grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.en
dc.subject.classificationComputer and Information Scienceen
dc.subject.keywordComputer network architecturesen
dc.subject.keywordComputer architecturesen
dc.subject.keywordMultiprocessorsen
dc.subject.keywordParallel processingen
dc.subject.keywordHierarchical Network of Hypercubesen
dc.titleArchitecture, Performance and Applications of a Hierarchial Network of Hypercubesen
dc.typeElectronic Thesis and Dissertationen
dc.degree.namePhDen
dc.degree.levelDoctoralen
dc.degree.grantorIndian Institute of Scienceen
dc.degree.disciplineFaculty of Engineeringen


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