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dc.contributor.advisorKoteswara Rao, K S R
dc.contributor.authorKumar, Arvind
dc.date.accessioned2018-07-14T06:32:18Z
dc.date.accessioned2018-07-31T06:20:02Z
dc.date.available2018-07-14T06:32:18Z
dc.date.available2018-07-31T06:20:02Z
dc.date.issued2018-07-14
dc.date.submitted2016
dc.identifier.urihttp://etd.iisc.ac.in/handle/2005/3820
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/4691/G28261-Abs.pdfen_US
dc.description.abstractThe continuous downscaling has enforced the device size and oxide thickness to few nanometers. After serving for several decades as an excellent gate oxide layer in complementary metal oxide semiconductor (CMOS) devices, the thickness of SiO2 layer has reached to its theoretical limits. Ultra-thin films of SiO2 can result in severe leakage currents due to direct tunneling as well as maintaining the homogeneity of the layers becomes an additional challenge. The use of a high- (HK) layer can solve these twin concerns of the semiconductor industry, which can also enhance the capacitance due to superior dielectric permittivity and reduce the leakage current by being thicker than the silicon dioxide. This thesis is concerned about the development of solution route fabricated high-k (TiO2, ZrO2 and HfO2) gate dielectrics and the investigation of high-/silicon interfaces by highly sensitive DLTS technique in MOS structures. The solution processing reduce the industrial fabrication cost and the DLTS method has the advantage to accurately measure the interface related defects parameters; such as interface trap density (Dit), capture cross-section (), activation energy (ET) and also distinguish between bulk and interface traps. In this thesis, HK films have been deposited by solution route, the material and electrical properties of the film and the HK/Si interface have been extensively evaluated. IN CHAPTER 1, we have summarized the history and evolution of transistor and it provides the background for the work presented in this thesis. IN CHAPTER 2, we have described the experimental method /technique used for the fabrication and characterization. The advantages and working principals of spin-coating and DLTS techniques are summarized. IN CHAPTER 3, we have presented the preparation and optimization of TiO2 based HK layer. Structural, surface morphology, optical electrical and dielectric properties are discussed in details. A high- 34 value is achieved for the 36 nm TiO2 films. IN CHAPTER 4, we presented the technologically relevant Si/TiO2 interface study by DLTS technique. The DLTS analysis reveals a small capture cross-section of the interface with acceptable interface state density. IN CHAPTER 5, we have focused on the fabrication of amorphous ZrO2 films on p-Si substrate. The advantage of amorphous dielectric layer is summarized as first dielectric reported SiO2 is used in its amorphous phase. The moderate-15 with low leakage current density is achieved. IN CHAPTER 6, the HfO2 films are prepared using hafnium isopropoxide and a high value of dielectric constant 23 is optimized with low leakage current density. The current conduction mechanisms are discussed in details. IN CHAPTER 7, we have probed the oxygen vacancy related sub-band-gap states in HfO2 by DLTS technique. IN CHAPTER 8, we have presented the summary of the dissertation and the prospect research directions are suggested. In summary, we have studied the group IVB transition metal elemental oxides (TMEO); TiO2, ZrO2 and HfO2 thin films in the MOS structure, as a possible replacement of SiO2 gate dielectric. For the TMEO films deposition a low-cost and simple method spin-coating was utilized. The film thicknesses are in the range of 35 – 39 nm, which was measured by ellipsometry and confirmed with the cross-sectional SEM. A rough surface of gate dielectric layer can trap the charge carrier and may cause the Fermi level pinning, which can cause the threshold voltage instabilities. Hence, surface roughness of oxide layer play an important role in CMOS device operation. We have achieved quite good flat surfaces (RMS surface roughness’s are 0.2 – 2.43 nm) for the films deposited in this work. The TiO2 based MOS gate stack shows an optimized high dielectric constant ( 34) with low leakage current density (3.710-7 A.cm-2 at 1 V). A moderate dielectric constant ( 15) with low leakage current density (4.710-9 A.cm-2 at 1 V) has been observed for the amorphous ZrO2 thin films. While, HfO2 based MOS gate stack shows reasonably high dielectric constant ( 23) with low leakage current density (1.410-8 A.cm-2 at 1 V). We have investigated the dominating current conduction mechanism and found that the current is mainly governed by space charge limited conduction (SCLC) mechanism for the high bias voltages, while low and intermediate bias voltages show the (Poole – Frenkel) PF and (Fowler – Nordheim) FN tunneling, respectively. For the HfO2 MOS device band alignment is drawn from the UPS and J-V measurements. The band gap and electron affinity of HfO2 films are estimated 5.9 eV and 3 eV, respectively, which gives a reasonable conduction band offset (1.05 eV) with respect to Si. A TMEO film suffers from a large number of intrinsic defects, which are mostly oxygen vacancies. These defects can create deep levels below the conduction band of high- dielectric material, which can act like a hole and electron traps. In addition to that, interface between Si and high- is an additional concern. These defect states in the band gap of high- or at the Si/ high- interface might lead to the threshold voltage shifts, lower carrier mobility in transistor channel, Fermi level pinning and various other reliability issues. Hence, we also studied bulk and interfacial defects present in the high- films on Si and their interface with Si by a very sensitive DLTS technique. The capture cross-sections are measured by insufficient filling DLTS (IF – DLTS). The defects present at the interface are Si dandling bond and defect in the bulk are mostly oxygen vacancies related defects present in various charge states. The interface states (Dit) are in the range of 2×1011 to 9×1011 eV-1cm-2, which are higher than the Al/SiO2/Si MOS devices (Dit in Al/SiO2/Si is the benchmark and in the order of 1010 eV-1cm-2). Still this is an acceptable value for Si/high-k (non-native oxide) MOS devices and consistent with other deposition methods. The capture cross-sections are found to be quite low in the order of 10-18 to 10-19 cm2, which indicate a minor impact on the device operation. The small value of capture cross-sections are attributed to the involvement of tunneling, to and from the bulk traps to the interface. In conclusion, the low cost solution processed high- thin films obtained are of high quality and find their importance as a potential dielectric layer. DLTS study will be helpful to reveal various interesting facts observed in high- such as resistive switching, magnetism and leakage current problems mediated by oxygen vacancy related defectsen_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG28261en_US
dc.subjectMetal Oxide Semiconductors - Silicon Interfacesen_US
dc.subjectMetal Oxide Semiconductorsen_US
dc.subjectMetal Oxide Semiconductors Deep Level Transient Spectroscopyen_US
dc.subjectIntegrated Circuiten_US
dc.subjectThermal Stabilityen_US
dc.subjectThermal Evaporationen_US
dc.subjectHigh-κ Gate Dielectricsen_US
dc.subjectHigh-κ TiO2 MOS Structuresen_US
dc.subjectHigh-κ Titania Thin Filmsen_US
dc.subjectHigh-k ZrO2 Gate Dielectricsen_US
dc.subjectSpin-coated HfO2 Thin Filmsen_US
dc.subjectHigh-κ TiO2 Thin Filmsen_US
dc.subjectHigh-κ ZrO2/Si MOS Structureen_US
dc.subjectSol-gel Spin-coating Methoden_US
dc.subject.classificationPhysicsen_US
dc.titleFacile and Process Compatible Growth of High-k Gate Dielectric Materials (TiO2, ZrO2 and HfO2) on Si and the Investigation of these Oxides and their Interfaces by Deep Level Transient Spectroscopyen_US
dc.typeThesisen_US
dc.degree.namePhDen_US
dc.degree.levelDoctoralen_US
dc.degree.disciplineFaculty of Scienceen_US


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