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    RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture 

    Satrawala, Amar Nath (2011-01-20)
    REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation ...

    Automatic Generation Of Compiled Cycle Level Microarchitecture Simulators For Superspeculative Processors 

    Chandran, Priya (2011-07-25)

    Adaptive Grid Meta Scheduling - A QoS Perspective 

    Nainwal, Kalash Chandra (2011-09-06)

    Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors 

    Valluri, Madhavi Gopal (2011-11-16)

    Performance Measurement Of A Java Virtual Machine 

    Pramod, B S (2011-11-16)

    Holistic Source-centric Schema Mappings For XML-on-RDBMS 

    Patil, Priti (2011-09-07)

    Efficient Resource Usage Modelling 

    Ramanan, V Janaki (2011-11-16)

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    AuthorChandran, Priya (1)Nainwal, Kalash Chandra (1)Patil, Priti (1)Pramod, B S (1)Ramanan, V Janaki (1)Satrawala, Amar Nath (1)Valluri, Madhavi Gopal (1)Subject
    Computer Science (7)
    Compilers (3)Computer Architecture (2)Adaptive Grid Meta Scheduling (1)August System (1)Automatic Simulator Generator (1)Coarse Grain (1)Compiling (Electronic Computers) (1)Computer Architecture - Modeling (1)Computer Simulation (1)... View MoreDate Issued
    2011 (7)
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    Yes (7)

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