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dc.contributor.advisorNarayanan, G
dc.contributor.authorGopalakrishnan, K S
dc.date.accessioned2017-05-24T16:26:52Z
dc.date.accessioned2018-07-31T04:56:53Z
dc.date.available2017-05-24T16:26:52Z
dc.date.available2018-07-31T04:56:53Z
dc.date.issued2017-05-24
dc.date.submitted2013-07
dc.identifier.urihttp://etd.iisc.ac.in/handle/2005/2628
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/3382/G25997-Abs.pdfen_US
dc.description.abstractThree-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.en_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG25997en_US
dc.subjectVoltage Source Invertersen_US
dc.subjectElectrolytic Capacitorsen_US
dc.subjectCapacitor Currenten_US
dc.subjectElectric Invertersen_US
dc.subjectPulse Width Modulation (PWM)en_US
dc.subjectDc-Link Capacitor Currenten_US
dc.subjectDC Electrolytic Capacitoren_US
dc.subjectSpace-Vector Pulse Width Modulationen_US
dc.subjectCapacitor Power Lossen_US
dc.subjectCapacitor Voltage Rippleen_US
dc.subjectCapacitor RMS (Root Mean Square) Currenten_US
dc.subjectCentered Space Vector Pulse Width Modulation (CSVPWM)en_US
dc.subjectDiode Clamped Invertersen_US
dc.subjectSine-triangle Pulse Width Modulation (SPWM)en_US
dc.subjectRMS Currenten_US
dc.subjectThree-Level Diode-Clamped Invertersen_US
dc.subjectDiode-clamped VSIen_US
dc.subject.classificationPower Electronicsen_US
dc.titleStudy On DC-Link Capacitor Current In A Three-Level Neutral-Point Clamped Inverteren_US
dc.typeThesisen_US
dc.degree.nameMSc Enggen_US
dc.degree.levelMastersen_US
dc.degree.disciplineFaculty of Engineeringen_US


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