Now showing items 1-8 of 8
RETHROTTLE : Execution Throttling In The REDEFINE SoC Architecture
REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation ...
Cache Coherence State Based Replacement Policies
Cache replacement policies can play a pivotal role in the overall performance of a system by preserving data locality and thus limiting the o -chip accesses. In a shared memory system, a cache coherence protocol is necessary ...
Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm
Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using a ...
Cooperative Execution of Opencl Programs on Multiple Heterogeneous Devices
Computing systems have become heterogeneous with the increasing prevalence of multi-core CPUs, Graphics Processing Units (GPU) and other accelerators in them. OpenCL has emerged as an attractive programming framework for ...
Adaptive Grid Meta Scheduling - A QoS Perspective
Hardware Consolidation Of Systolic Algorithms On A Coarse Grained Runtime Reconfigurable Architecture
Application domains such as Bio-informatics, DSP, Structural Biology, Fluid Dynamics, high resolution direction finding, state estimation, adaptive noise cancellation etc. demand high performance computing solutions for ...
CDMA Base Station Receive Co-Processor Architecture
Third generation mobile communication systems promise a greater data rate and new services to the mobile subscribers. 3G systems support up to 2 Mbps of data rate to a fixed subscriber and 144 Kbps of data rate to a fully ...