Now showing items 1-10 of 185
Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques
Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level ...
Learning Robust Support Vector Machine Classifiers With Uncertain Observations
The central theme of the thesis is to study linear and non linear SVM formulations in the presence of uncertain observations. The main contribution of this thesis is to derive robust classfiers from partial knowledge of ...
A Theoretical Study of the Synergy and Lazy Annotation Algorithms
Given a program with assertions, the assertion checking problem is to tell whether there is an execution of the program that violates one of the assertions. One approach to this problem is to explore different paths towards ...
Falcon : A Graph Manipulation Language for Distributed Heterogeneous Systems
Graphs model relationships across real-world entities in web graphs, social network graphs, and road network graphs. Graph algorithms analyze and transform a graph to discover graph properties or to apply a computation. ...
Large Data Clustering And Classification Schemes For Data Mining
Data Mining deals with extracting valid, novel, easily understood by humans, potentially useful and general abstractions from large data. A data is large when number of patterns, number of features per pattern or both are ...
Low Power Test Methodology For SoCs : Solutions For Peak Power Minimization
Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power ...
A Study Of Quantum And Reversible Computing
Optimizations In Storage Area Networks And Direct Attached Storage
The thesis consists of three parts. In the first part, we introduce the notion of device-cache-aware schedulers. Modern disk subsystems have many megabytes of memory for various purposes such as prefetching and caching. ...
Improving Last-Level Cache Performance in Single and Multi-Core Processsors
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a timely fashion remains one of the key performance bottlenecks in current systems. With increasing core counts, this problem ...