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Spill Code Minimization And Buffer And Code Size Aware Instruction Scheduling Techniques
Instruction scheduling and Software pipelining are important compilation techniques which reorder instructions in a program to exploit instruction level parallelism. They are essential for enhancing instruction level ...
Integrated Scheduling For Clustered VLIW Processors
(Indian Institute of Science, 2005-11-25)
Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Scheduling for clustered architectures ...