Show simple item record

dc.contributor.advisorJamadagni, H S
dc.contributor.authorLata, Kusum
dc.date.accessioned2011-07-08T11:16:20Z
dc.date.accessioned2018-07-31T04:34:16Z
dc.date.available2011-07-08T11:16:20Z
dc.date.available2018-07-31T04:34:16Z
dc.date.issued2011-07-08
dc.date.submitted2010
dc.identifier.urihttps://etd.iisc.ac.in/handle/2005/1271
dc.identifier.abstracthttp://etd.iisc.ac.in/static/etd/abstracts/1652/G23821-Abs.pdfen_US
dc.description.abstractThe conventional approach to validate the analog and mixed signal designs utilizes extensive SPICE-level simulations. The main challenge in this approach is to know when all important corner cases have been simulated. An alternate approach is to use the formal verification techniques. Formal verification techniques have gained wide spread popularity in the digital design domain; but in case of analog and mixed signal designs, a large number of test scenarios need to be designed to generate sufficient simulation traces to test out all the specified system behaviours. Analog and mixed signal designs can be formally modeled as hybrid systems and therefore techniques used for formal analysis and verification of hybrid systems can be applied to the analog and mixed signal designs. Generally, formal verification tools for hybrid systems work at the abstract level where we model the systems in terms of differential equations or algebraic equations. However the analog and mixed signal system designers are very comfortable in designing the circuits at the transistor level. To bridge the gap between abstraction level verification and the designs validation which has been implemented at the transistor level, the very important issue we need to address is: Can we formally verify the circuits at the transistor level itself? For this we have proposed a framework for doing the formal verification of analog and mixed signal designs using SPICE simulation traces in one of the hybrid systems formal verification tools (i.e. Checkmate from CMU). An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design to be also used for validating its different refinements and design implementation, thereby providing a simple route to formal verification at different levels of implementation. Our approach has been illustrated through the case studies using simulation traces form the different frameworks i.e. Simulink/Stateflow framework and the SPICE simulation traces. We demonstrate the feasibility of our approach around the Checkmate and the case studies for hybrid systems and the analog and mixed signal designs.en_US
dc.language.isoen_USen_US
dc.relation.ispartofseriesG23821en_US
dc.subjectSignal Processing - Simulationen_US
dc.subjectHybrid System Verificationen_US
dc.subjectAnalog and Mixed Signal Design Verificationen_US
dc.subjectFormal Verificationen_US
dc.subjectCheckmate Formal Verificationen_US
dc.subjectIntegrated Circuits - Simulationen_US
dc.subjectDigital Simulationen_US
dc.subjectAutomataen_US
dc.subjectHybrid Automataen_US
dc.subjectHybrid Systemsen_US
dc.subjectAMS Designsen_US
dc.subjectAnalog and Mixed Signal Designsen_US
dc.subject.classificationCommunication Engineeringen_US
dc.titleFormal Verification Of Analog And Mixed Signal Designs Using Simulation Tracesen_US
dc.typeThesisen_US
dc.degree.namePhDen_US
dc.degree.levelDoctoralen_US
dc.degree.disciplineFaculty of Engineeringen_US


Files in this item

This item appears in the following Collection(s)

Show simple item record