| dc.contributor.advisor | Jamadagni, H S | |
| dc.contributor.author | Balssubramanian, Suresh | |
| dc.date.accessioned | 2011-04-13T03:59:32Z | |
| dc.date.accessioned | 2018-07-31T04:34:08Z | |
| dc.date.available | 2011-04-13T03:59:32Z | |
| dc.date.available | 2018-07-31T04:34:08Z | |
| dc.date.issued | 2011-04-13 | |
| dc.date.submitted | 2004 | |
| dc.identifier.uri | https://etd.iisc.ac.in/handle/2005/1127 | |
| dc.identifier.abstract | http://etd.iisc.ac.in/static/etd/abstracts/1477/G19577-Abs.pdf | en_US |
| dc.language.iso | en_US | en_US |
| dc.relation.ispartofseries | G19577 | en_US |
| dc.subject | Computer Aided Design | en_US |
| dc.subject | Integrated Circuits | en_US |
| dc.subject | Phased Locked Loop | en_US |
| dc.subject | Phased Locked Loop Design - Behavioral Models | en_US |
| dc.subject | PLL Design | en_US |
| dc.subject | Digital Signal Processing (DSP) | en_US |
| dc.subject | Application Specific Integrated Circuits (ASIC) | en_US |
| dc.subject | Phase Frequency Detector (PFD) | en_US |
| dc.subject | Voltage Controlled Oscillators (VCO) | en_US |
| dc.subject.classification | Electronic Engineering | en_US |
| dc.title | Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models | en_US |
| dc.type | Thesis | en_US |
| dc.degree.name | MSc Engg | en_US |
| dc.degree.level | Masters | en_US |
| dc.degree.discipline | Faculty of Engineering | en_US |
